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testbench.sv

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Feb 19th, 2019
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  1. module testbench();
  2.  
  3. timeunit 10ns;// Half clock cycle at 50 MHz
  4.             // This is the amount of time represented by #1
  5.  
  6. timeprecision 1ns;
  7.  
  8. // These signals are internal because the processor will be
  9. // instantiated as a submodule in testbench.
  10. logic [15:0] S;
  11. logic   Clk, Reset, Run, Continue;
  12. logic [11:0] LED;
  13. logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7; //added HEX4 to HEX7 to make compiler happy but I'm not sure if we need all these
  14.  
  15. logic CE, UB, LB, OE, WE;
  16. logic [19:0] ADDR;
  17. wire [15:0] Data;
  18.  
  19. // Instantiating the DUT
  20. // Make sure the module and signal names match with those in your design
  21. lab6_toplevel CPU (.*);
  22.                
  23. // A counter to count the instances where simulation results
  24. // do no match with expected results
  25.  
  26. // Toggle the clock
  27. // #1 means wait for a delay of 1 timeunit
  28. always begin: CLOCK_GENERATION
  29. #1 Clk = ~Clk;
  30. end
  31.  
  32. initial begin: CLOCK_INITIALIZATION
  33.     Clk = 0;
  34. end
  35.  
  36. /*always begin: INTERNAL_MONITORING
  37. #2 PC = CPU.cpu.d0.PC_REG.OUT;
  38. MDR = CPU.cpu.d0.MDR_REG.OUT;
  39. MAR = CPU.cpu.d0.MAR_REG.OUT;
  40. IR = CPU.cpu.d0.IR_REG.OUT;
  41. end*/
  42.  
  43. // Testing begins here
  44. // The initial block is not synthesizable
  45. // Everything happens sequentially inside an initial block
  46. // as in a software program
  47. initial begin: TEST_VECTORS
  48. Reset = 0;      // reset system
  49. Run = 1;            // keep run low
  50. Continue = 1;
  51.  
  52. #2 Reset = 1;       // stop reset
  53.    
  54. #2 Run = 0;             // run
  55. #2 Run = 1;
  56.  
  57. #6 Continue = 0;
  58. #2 Continue = 1;
  59.  
  60. #6 Continue = 0;
  61. #2 Continue = 1;
  62.  
  63. #6 Continue = 0;
  64. #2 Continue = 1;
  65.  
  66. #6 Continue = 0;
  67. #2 Continue = 1;
  68.  
  69. #6 Continue = 0;
  70. #2 Continue = 1;
  71.  
  72. #6 Continue = 0;
  73. #2 Continue = 1;
  74.  
  75. #6 Continue = 0;
  76. #2 Continue = 1;
  77.  
  78. #6 Continue = 0;
  79. #2 Continue = 1;
  80.  
  81.  
  82. #6 Continue = 0;
  83. #2 Continue = 1;
  84.  
  85.  
  86. #6 Continue = 0;
  87. #2 Continue = 1;
  88.  
  89.  
  90. #6 Continue = 0;
  91. #2 Continue = 1;
  92.  
  93.  
  94. #6 Continue = 0;
  95. #2 Continue = 1;
  96.  
  97. #6 Continue = 0;
  98. #2 Continue = 1;
  99.  
  100. #6 Continue = 0;
  101. #2 Continue = 1;
  102.  
  103. #6 Continue = 0;
  104. #2 Continue = 1;
  105.  
  106. #6 Continue = 0;
  107. #2 Continue = 1;
  108.  
  109. #6 Continue = 0;
  110. #2 Continue = 1;
  111.  
  112. #6 Continue = 0;
  113. #2 Continue = 1;
  114.  
  115.  
  116. end
  117.  
  118. endmodule
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