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  1. IntBase_Dly_Clk        <= IntRx_SysClk;
  2. ---------------------------------------------------------------------------------------------
  3. -- Use of PHY_RDEN.
  4. -- Use of PHY_RDEN is TIME and MIG and thus these signals must be tied HIGH all the time
  5. IntBase_Tx_Phy_Rden <= LowVec(3 downto 0);
  6. IntBase_Rx_Phy_Rden <= HighVec(3 downto 0);
  7. ---------------------------------------------------------------------------------------------
  8. -- # Clock Reset - RIU State machine
  9. -- In the non-wizard design the clocking and RIU stuff happens from within the Clock_Reset
  10. -- hierarchical block. But in the the wizard design the Clock_Reset hierarchical block is
  11. -- not needed since PLL and reset sequencers are included in the cores.
  12. -- What is not included in the cores is the RIU accessing state machine, so that has been
  13. -- extracted from the Clock_Reset block and is used here in with the wizard design.
  14. -- The *Clock_Reset.vhd* source can be found in the /Libraries/clkrst_lib folder.
  15. -- The *Riu_StateMach.vhd* can also be found in that folder.
  16. --
  17. -- The clocks of the *Riu_StateMach* hierarchical block are no longer outputs but inputs.
  18. -- Why? Well:
  19. -- All PLL and reset stuff is assembled into the IO IP cores generated by the HSSIO-Wiz.
  20. -- Since clocks are no longer generated together with the state machine, the clocks
  21. -- for the state machine need to come from outside the file, from the IP cores.
  22. --
  23. -- ## Pin and attribute description
  24. --  - C_InSimulation  : Attribute to force the RIU state machine in a simulation mode.
  25. --                    : the state machine is partially overrules and only provides Fixed
  26. --                    : values form the read registers.
  27. --  - ClockIn         : RIU clock input, must be supplied by the HSSIO core
  28. --  - ResetIn         : Reset input from external, goes also the the HSSIO cores
  29. --  - Tx_Dly_Rdy      : TX: Input from the HSSO core (BITSLICE_CONTROL output).
  30. --  - Tx_Vtc_Rdy      : TX: Input from the HSSO core (BITSLICE_CONTROL output).
  31. --  - Tx_Bsc_EnVtc    : TX: Output to the HSSIO core (input for the BISTLICE_CONTROL).
  32. --  - Tx_Bs_EnVtc     : TX: Output to the bitslices (Input for the BITSLICEs).
  33. --  - Rx_Dly_Rdy      : RX: Input from the HSSO core (BITSLICE_CONTROL output).
  34. --  - Rx_Vtc_Rdy      : RX: Input from the HSSO core (BITSLICE_CONTROL output).
  35. --  - Rx_Bsc_EnVtc    : RX: Output to the HSSIO core (input for the BISTLICE_CONTROL).
  36. --  - Rx_Bs_EnVtc     : RX: Output to the bitslices (Input for the BITSLICEs).
  37. --  - Tx_WrClk        : input, Application clock generated by the TX HSSIO core PLL
  38. --  - Rx_SysClk       : input, Application clock generated by the RX HSSIO core PLL
  39. --  - Tx_Locked       : Input, signal generated by the HSSIO core.
  40. --  - Rx_Locked       : Input, signal generated by the HSSIO core.
  41. --  - Tx_LogicRst     : output, Reset for application logic generated by the state machine.
  42. --  - Rx_LogicRst     : output, Reset for application logic generated by the state machine.
  43. --  - Riu_*           : RIU access ports.
  44. --                    : There is one RIU per nibble, thus two RIU per byte.
  45. --  - Riu_Prsnt       : Input, normally indicates if a RIU interface is present.
  46. --                    : Not used in the HSSIO cores. RIU presence is there set
  47. --                    : by a tick-box in the wizard.
  48. --                    : The signals are tied high or low in an upper level.
  49. --============================================================================================
  50. Byte_TopWizard_RxTx_I_Riu_StateMach : entity clkrst_lib.Riu_StateMach
  51.     generic map (
  52.         C_InSimulation      => C_InSimulation
  53.     )
  54.     port map (
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