Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- `include "mult_signed_clk.v"
- `timescale 1us/1us
- module mult_tb_signed;
- // on testbenches, inputs are regs
- reg signed [3:0] in1;
- reg signed [3:0] in2;
- reg clk;
- // on testbenches, outputs are wires
- wire signed [4:0] out;
- mult_signed MULT1(in1,in2,clk, out);
- initial begin
- clk = 0; in1 = -8; in2 = -8;
- #(2+2*2**8) $finish;
- end // initial begin
- always #1 clk = ~clk;
- always #2 in1 = in1+1;
- always #(2*2**4) in2 = in2+1;
- initial begin
- $monitor ("%t | in1 = %d | in2 = %d | clk = %d | out = %d", $time, in1, in2, clk, out);
- $dumpfile("dump.vcd");
- $dumpvars();
- end
- endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement