First failing ddr path

Timing constraint: TS_crg_pll_2_ = PERIOD TIMEGRP "crg_pll_2_" TS_crg_clk100b / 1.5 PHASE         3.88888889 ns HIGH 50%;
 For more information, see Period Analysis in the Timing Closure User Guide (UG612).
  339 paths analyzed, 260 endpoints analyzed, 1 failing endpoint
  1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
  Minimum period is   6.683ns.
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 Paths for end point ddrphy_record1_address_5 (SLICE_X41Y60.B1), 3 paths
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 Slack (setup path):     -0.010ns (requirement - (data path - clock path skew + uncertainty))
   Source:               lm32_cpu/load_store_unit/d_adr_o_6 (FF)
   Destination:          ddrphy_record1_address_5 (FF)
   Requirement:          3.888ns
   Data Path Delay:      3.261ns (Levels of Logic = 2)
   Clock Path Skew:      -0.413ns (2.024 - 2.437)
   Source Clock:         sys_clk rising at 0.000ns
   Destination Clock:    sdram_half_clk rising at 3.888ns
   Clock Uncertainty:    0.224ns

   Clock Uncertainty:          0.224ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.070ns
     Discrete Jitter (DJ):       0.195ns
     Phase Error (PE):           0.120ns

   Maximum Data Path at Slow Process Corner: lm32_cpu/load_store_unit/d_adr_o_6 to ddrphy_record1_address_5
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X39Y51.BQ      Tcko                  0.430   lm32_cpu/load_store_unit/d_adr_o<8>
                                                        lm32_cpu/load_store_unit/d_adr_o_6
     SLICE_X41Y56.B6      net (fanout=3)        0.832   lm32_cpu/load_store_unit/d_adr_o<6>
     SLICE_X41Y56.B       Tilo                  0.259   basesoc_grant1
                                                        lut5103_564_1
     SLICE_X41Y60.B1      net (fanout=2)        1.367   lut5103_5641
     SLICE_X41Y60.CLK     Tas                   0.373   ddrphy_record0_address<4>
                                                        ][8258_2600
                                                        ddrphy_record1_address_5
     -------------------------------------------------  ---------------------------
     Total                                      3.261ns (1.062ns logic, 2.199ns route)
                                                        (32.6% logic, 67.4% route)