fbox{
begin{minipage}{linewidth}
small
begin{verbatim}

[2018-05-25 19:21:48 EDT] iverilog '-Wall' design.sv testbench.sv  && unbuffer vvp a.out
a=  2, b=  5, outsum=  7, true_sum=  7, cout=0
a=  2, b= 34, outsum= 36, true_sum= 36, cout=0
a=  2, b= 63, outsum= 65, true_sum= 65, cout=0
a=  2, b= 92, outsum= 94, true_sum= 94, cout=0
a=  2, b=121, outsum=123, true_sum=123, cout=0
a=  2, b=150, outsum=152, true_sum=152, cout=0
a=  9, b=  5, outsum= 14, true_sum= 14, cout=0
a=  9, b= 34, outsum= 43, true_sum= 43, cout=0
a=  9, b= 63, outsum= 72, true_sum= 72, cout=0
a=  9, b= 92, outsum=101, true_sum=101, cout=0
a=  9, b=121, outsum=130, true_sum=130, cout=0
a=  9, b=150, outsum=159, true_sum=159, cout=0
a= 16, b=  5, outsum= 21, true_sum= 21, cout=0
a= 16, b= 34, outsum= 50, true_sum= 50, cout=0
a= 16, b= 63, outsum= 79, true_sum= 79, cout=0
a= 16, b= 92, outsum=108, true_sum=108, cout=0
a= 16, b=121, outsum=137, true_sum=137, cout=0
a= 16, b=150, outsum=166, true_sum=166, cout=0
Done
end{verbatim}

end{minipage}}

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