17

`timescale 1ns / 1ps

module top(
    input [1:0] in,
    input clk,
    input rst,
    output out
    );

parameter S0=4'b0000, S1=4'b0001, S2=4'b0010, S3=4'b0011, S4=4'b0100, S5=4'b0101, S6=4'b0110, S7=4'b0111, S8=4'b1000;

reg [3:0] state = S0;
reg [3:0] nextstate = S0;
reg out_tmp = 1'bx;

always @(*) begin
	case( state )

		S0:
			case( in )
				2'b00:
					nextstate = S0;
				2'b01:
					nextstate = S1;
				2'b10:
					nextstate = S5;
				2'b11:
					nextstate = S0;
				default:
					nextstate = S0;
			endcase

		S1:
			case( in )
				2'b00:
					nextstate = S8;
				2'b01:
					nextstate = S1;
				2'b10:
					nextstate = S0;
				2'b11:
					nextstate = S2;
				default:
					nextstate = S0;
			endcase

		S2:
			case( in )
				2'b00:
					nextstate = S0;
				2'b01:
					nextstate = S7;
				2'b10:
					nextstate = S3;
				2'b11:
					nextstate = S2;
				default:
					nextstate = S0;
			endcase

		S3:
			case( in )
				2'b00:
					nextstate = S4;
				2'b01:
					nextstate = S0;
				2'b10:
					nextstate = S3;
				2'b11:
					nextstate = S6;
				default:
					nextstate = S0;
			endcase

		S4:
			case( in )
				2'b00:
					nextstate = S4;
				2'b01:
					nextstate = S1;
				2'b10:
					nextstate = S5;
				2'b11:
					nextstate = S0;
				default:
					nextstate = S0;
			endcase

		S5:
			case( in )
				2'b00:
					nextstate = S4;
				2'b01:
					nextstate = S0;
				2'b10:
					nextstate = S5;
				2'b11:
					nextstate = S6;
				default:
					nextstate = S0;
			endcase

		S6:
			case( in )
				2'b00:
					nextstate = S0;
				2'b01:
					nextstate = S7;
				2'b10:
					nextstate = S3;
				2'b11:
					nextstate = S6;
				default:
					nextstate = S0;
			endcase

		S7:
			case( in )
				2'b00:
					nextstate = S8;
				2'b01:
					nextstate = S7;
				2'b10:
					nextstate = S0;
				2'b11:
					nextstate = S2;
				default:
					nextstate = S0;
			endcase

		S8:
			case( in )
				2'b00:
					nextstate = S8;
				2'b01:
					nextstate = S1;
				2'b10:
					nextstate = S5;
				2'b11:
					nextstate = S0;
				default:
					nextstate = S0;
			endcase

		default:
			nextstate = S0;
	endcase
end

always @( posedge clk ) begin
	if( rst == 1'b1 ) begin
		state <= S0;
	end
		else begin
			state <= nextstate;
		end
end

always @(*) begin
	if( state == S1 || state == S2 || state == S3 || state == S4 ) begin
		out_tmp <= 1'b0; // LEFT
	end
		else if( state == S5 || state == S6 || state == S7 || state == S8 ) begin
			out_tmp <= 1'b1; // RIGHT
		end
			else begin
				out_tmp <= 1'bx; // UNKNOWN
			end
end

assign out = out_tmp;

endmodule