ffjk_tb

-- Descrição do testbench do flip-flop JK
library ieee;
use ieee.std_logic_1164.all;

entity ffjk_tb is
end ffjk_tb;

architecture teste of ffjk_tb is
component ffjk
    port(
        j: in std_logic;
        k: in std_logic;
        clk: in std_logic;
        clr: in std_logic;
        q: out std_logic
    );
end component;
signal jj: std_logic := '0';
signal kk: std_logic := '0';
signal clock: std_logic := '0';
signal clear: std_logic := '1';
signal qq: std_logic;
begin
    flip_flop: ffjk port map (jj,kk,clock,clear,qq);
    process (clock)
    begin
        clock <= not clock after 10 ns;
    end process;
    clear <= '0' after 10 ns, '1' after 50 ns;
    jj <= '1' after 10 ns, '0' after 70 ns, '1' after 110 ns;
    kk <= '1' after 30 ns, '0' after 50 ns, '1' after 70 ns, '0' after 90 ns, '1' after 110 ns;
end teste;