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system_stm32f4xx_c_olimex_E407.patch

sparcz Oct 1st, 2012 544 Never
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  1. --- system_stm32f4xx.orig.c     2012-09-17 13:20:00.000000000 +0200
  2. +++ system_stm32f4xx.c  2012-09-28 00:43:32.000000000 +0200
  3. @@ -2,12 +2,12 @@
  4.    ******************************************************************************
  5.    * @file    system_stm32f4xx.c
  6.    * @author  MCD Application Team
  7. -  * @version V1.0.0
  8. -  * @date    19-September-2011
  9. +  * @version V1.0.1
  10. +  * @date    28-September-2012
  11.    * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
  12.    *          This file contains the system clock configuration for STM32F4xx devices,
  13.    *          and is generated by the clock configuration tool
  14. -  *          stm32f4xx_Clock_Configuration_V1.0.0.xls
  15. +  *          stm32f4xx_Clock_Configuration_V1.0.1.xls
  16.    *            
  17.    * 1.  This file provides two functions and one global variable to be called from
  18.    *     user application:
  19. @@ -34,7 +34,7 @@
  20.    *    function will do nothing and HSI still used as system clock source. User can
  21.    *    add some code to deal with this issue inside the SetSysClock() function.
  22.    *
  23. -  * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
  24. +  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
  25.    *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
  26.    *    through PLL, and you are using different crystal you have to adapt the HSE
  27.    *    value to your own configuration.
  28. @@ -56,9 +56,9 @@
  29.    *-----------------------------------------------------------------------------
  30.    *        APB2 Prescaler                         | 2
  31.    *-----------------------------------------------------------------------------
  32. -  *        HSE Frequency(Hz)                      | 8000000
  33. +  *        HSE Frequency(Hz)                      | 12000000
  34.    *-----------------------------------------------------------------------------
  35. -  *        PLL_M                                  | 8
  36. +  *        PLL_M                                  | 12
  37.    *-----------------------------------------------------------------------------
  38.    *        PLL_N                                  | 336
  39.    *-----------------------------------------------------------------------------
  40. @@ -66,15 +66,23 @@
  41.    *-----------------------------------------------------------------------------
  42.    *        PLL_Q                                  | 7
  43.    *-----------------------------------------------------------------------------
  44. -  *        PLLI2S_N                               | NA
  45. +  *        PLLI2S_N                               | 271
  46.    *-----------------------------------------------------------------------------
  47. -  *        PLLI2S_R                               | NA
  48. +  *        PLLI2S_R                               | 6
  49.    *-----------------------------------------------------------------------------
  50. -  *        I2S input clock                        | NA
  51. +  *        I2S input clock(Hz)                    | 45000000
  52. +  *                                               |
  53. +  *        To achieve the following I2S config:   |
  54. +  *         - Master clock output (MCKO): ON      |
  55. +  *         - Frame wide                : 16bit   |
  56. +  *         - Audio sampling freq (KHz) : 44,1    |
  57. +  *         - Error %                   : 0,0000  |
  58. +  *         - Prescaler Odd factor (ODD): 0       |
  59. +  *         - Linear prescaler (DIV)    : 2       |
  60.    *-----------------------------------------------------------------------------
  61. -  *        VDD(V)                                 | 3.3
  62. +  *        VDD(V)                                 | 3,3
  63.    *-----------------------------------------------------------------------------
  64. -  *        High Performance mode                  | Enabled
  65. +  *        Main regulator output voltage          | Scale1 mode
  66.    *-----------------------------------------------------------------------------
  67.    *        Flash Latency(WS)                      | 5
  68.    *-----------------------------------------------------------------------------
  69. @@ -132,6 +140,7 @@
  70.    * @{
  71.    */
  72.  
  73. +/************************* Miscellaneous Configuration ************************/
  74.  /*!< Uncomment the following line if you need to use external SRAM mounted
  75.       on STM324xG_EVAL board as data memory  */
  76.  /* #define DATA_IN_ExtSRAM */
  77. @@ -141,10 +150,11 @@
  78.  /* #define VECT_TAB_SRAM */
  79.  #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
  80.                                     This value must be a multiple of 0x200. */
  81. +/******************************************************************************/
  82.  
  83. -
  84. +/************************* PLL Parameters *************************************/
  85.  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
  86. -#define PLL_M      8
  87. +#define PLL_M      12
  88.  #define PLL_N      336
  89.  
  90.  /* SYSCLK = PLL_VCO / PLL_P */
  91. @@ -153,6 +163,13 @@
  92.  /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
  93.  #define PLL_Q      7
  94.  
  95. +/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
  96. +   I2SCLK = PLLI2S_VCO / PLLI2S_R */
  97. +#define PLLI2S_N   271
  98. +#define PLLI2S_R   6
  99. +
  100. +/******************************************************************************/
  101. +
  102.  /**
  103.    * @}
  104.    */
  105. @@ -203,6 +220,10 @@
  106.    */
  107.  void SystemInit(void)
  108.  {
  109. +  /* FPU settings ------------------------------------------------------------*/
  110. +  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  111. +    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  112. +  #endif
  113.    /* Reset the RCC clock configuration to the default reset state ------------*/
  114.    /* Set HSION bit */
  115.    RCC->CR |= (uint32_t)0x00000001;
  116. @@ -358,9 +379,9 @@
  117.  
  118.    if (HSEStatus == (uint32_t)0x01)
  119.    {
  120. -    /* Enable high performance mode, System frequency up to 168 MHz */
  121. +    /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
  122.      RCC->APB1ENR |= RCC_APB1ENR_PWREN;
  123. -    PWR->CR |= PWR_CR_PMODE;  
  124. +    PWR->CR |= PWR_CR_VOS;
  125.  
  126.      /* HCLK = SYSCLK / 1*/
  127.      RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
  128. @@ -400,6 +421,23 @@
  129.           configuration. User can add here some code to deal with this error */
  130.    }
  131.  
  132. +
  133. +/******************************************************************************/
  134. +/*                          I2S clock configuration                           */
  135. +/******************************************************************************/
  136. +  /* PLLI2S clock used as I2S clock source */
  137. +  RCC->CFGR &= ~RCC_CFGR_I2SSRC;
  138. +
  139. +  /* Configure PLLI2S */
  140. +  RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
  141. +
  142. +  /* Enable PLLI2S */
  143. +  RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);
  144. +
  145. +  /* Wait till PLLI2S is ready */
  146. +  while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
  147. +  {
  148. +  }
  149.  }
  150.  
  151.  /**
  152. @@ -496,14 +534,14 @@
  153.  
  154.    /* Configure and enable Bank1_SRAM2 */
  155.    FSMC_Bank1->BTCR[2]  = 0x00001015;
  156. -  FSMC_Bank1->BTCR[3]  = 0x00010603;//0x00010400;
  157. +  FSMC_Bank1->BTCR[3]  = 0x00010603;
  158.    FSMC_Bank1E->BWTR[2] = 0x0fffffff;
  159. -/*
  160. + /*
  161.    Bank1_SRAM2 is configured as follow:
  162.  
  163. -  p.FSMC_AddressSetupTime = 3;//0;
  164. +  p.FSMC_AddressSetupTime = 3;
  165.    p.FSMC_AddressHoldTime = 0;
  166. -  p.FSMC_DataSetupTime = 6;//4;
  167. +  p.FSMC_DataSetupTime = 6;
  168.    p.FSMC_BusTurnAroundDuration = 1;
  169.    p.FSMC_CLKDivision = 0;
  170.    p.FSMC_DataLatency = 0;
  171. @@ -524,8 +562,7 @@
  172.    FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
  173.    FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
  174.    FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
  175. -*/
  176. -  
  177. +*/  
  178.  }
  179.  #endif /* DATA_IN_ExtSRAM */
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