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May 20th, 2015
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  1. USB
  2. coreboot-4.0-9706-gda04dbc Wed May 20 18:51:40 UTC 2015 romstage starting...
  3. Setting up static southbridge registers... done.
  4. Disabling Watchdog reboot... done.
  5. Setting up static northbridge registers... done.
  6. Initializing Graphics...
  7. Back from sandybridge_early_initialization()
  8. SMBus controller enabled.
  9. CPU id(306a9): Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz
  10. AES supported, TXT supported, VT supported
  11. PCH type: QM77, device id: 1e55, rev id 4
  12. Intel ME early init
  13. Intel ME firmware is ready
  14. ME: Requested 32MB UMA
  15. Starting native Platform init
  16. ERROR: SPD CRC failed!!!CLC_CRC : 0
  17. SPD_CRC : ce66
  18. Revision: 11
  19. Type : b
  20. Key : 3
  21. Banks : 8
  22. Capacity: 4 Gb
  23. Supported voltages: 1.5V
  24. SDRAM width : 8
  25. Bus extension : 0 bits
  26. Bus width : 64
  27. Optional features : DLL-Off_mode RZQ/7 RZQ/6
  28. Thermal features : PASR ext_temp_range
  29. Thermal sensor : no
  30. Standard SDRAM : yes
  31. DIMM Reference card F
  32. Row addr bits : 16
  33. Column addr bits : 10
  34. Number of ranks : 2
  35. DIMM Capacity : 8192 MB
  36. CAS latencies : 6 7 8 9 10 11
  37. tCKmin : 1.250 ns
  38. tAAmin : 13.125 ns
  39. tWRmin : 15.000 ns
  40. tRCDmin : 13.125 ns
  41. tRRDmin : 6.000 ns
  42. tRPmin : 13.125 ns
  43. tRASmin : 35.000 ns
  44. tRCmin : 48.125 ns
  45. tRFCmin : 260.000 ns
  46. tWTRmin : 7.500 ns
  47. tRTPmin : 7.500 ns
  48. tFAWmin : 30.000 ns
  49. rankmap[0] = 0x3
  50. Not a DDR3 SPD!
  51. ERROR: SPD CRC failed!!!CLC_CRC : 0
  52. SPD_CRC : ce66
  53. Revision: 11
  54. Type : b
  55. Key : 3
  56. Banks : 8
  57. Capacity: 4 Gb
  58. Supported voltages: 1.5V
  59. SDRAM width : 8
  60. Bus extension : 0 bits
  61. Bus width : 64
  62. Optional features : DLL-Off_mode RZQ/7 RZQ/6
  63. Thermal features : PASR ext_temp_range
  64. Thermal sensor : no
  65. Standard SDRAM : yes
  66. DIMM Reference card F
  67. Row addr bits : 16
  68. Column addr bits : 10
  69. Number of ranks : 2
  70. DIMM Capacity : 8192 MB
  71. CAS latencies : 6 7 8 9 10 11
  72. tCKmin : 1.250 ns
  73. tAAmin : 13.125 ns
  74. tWRmin : 15.000 ns
  75. tRCDmin : 13.125 ns
  76. tRRDmin : 6.000 ns
  77. tRPmin : 13.125 ns
  78. tRASmin : 35.000 ns
  79. tRCmin : 48.125 ns
  80. tRFCmin : 260.000 ns
  81. tWTRmin : 7.500 ns
  82. tRTPmin : 7.500 ns
  83. tFAWmin : 30.000 ns
  84. rankmap[1] = 0x3
  85. Not a DDR3 SPD!
  86. PLL busy...done
  87. PLL didn't lock. Retrying at lower frequency
  88. PLL busy...done
  89. PLL didn't lock. Retrying at lower frequency
  90. PLL busy...done
  91. PLL didn't lock. Retrying at lower frequency
  92. PLL busy...done
  93. PLL didn't lock. Retrying at lower frequency
  94. No lock frequency foundUSB
  95. coreboot-4.0-9706-gda04dbc Wed May 20 18:51:40 UTC 2015 romstage starting...
  96. Setting up static southbridge registers... done.
  97. Disabling Watchdog reboot... done.
  98. Setting up static northbridge registers... done.
  99. Initializing Graphics...
  100. Back from sandybridge_early_initialization()
  101. SMBus controller enabled.
  102. CPU id(306a9): Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz
  103. AES supported, TXT supported, VT supported
  104. PCH type: QM77, device id: 1e55, rev id 4
  105. Intel ME early init
  106. Intel ME firmware is ready
  107. ME: Requested 32MB UMA
  108. Starting native Platform init
  109. ERROR: SPD CRC failed!!!CLC_CRC : 0
  110. SPD_CRC : ce66
  111. Revision: 11
  112. Type : b
  113. Key : 3
  114. Banks : 8
  115. Capacity: 4 Gb
  116. Supported voltages: 1.5V
  117. SDRAM width : 8
  118. Bus extension : 0 bits
  119. Bus width : 64
  120. Optional features : DLL-Off_mode RZQ/7 RZQ/6
  121. Thermal features : PASR ext_temp_range
  122. Thermal sensor : no
  123. Standard SDRAM : yes
  124. DIMM Reference card F
  125. Row addr bits : 16
  126. Column addr bits : 10
  127. Number of ranks : 2
  128. DIMM Capacity : 8192 MB
  129. CAS latencies : 6 7 8 9 10 11
  130. tCKmin : 1.250 ns
  131. tAAmin : 13.125 ns
  132. tWRmin : 15.000 ns
  133. tRCDmin : 13.125 ns
  134. tRRDmin : 6.000 ns
  135. tRPmin : 13.125 ns
  136. tRASmin : 35.000 ns
  137. tRCmin : 48.125 ns
  138.  
  139.  
  140. [it simply dies here]
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