`timescale 1ns/1ps
module counter_test;

integer i;
logicclk,ena,rst;
logic [3:0] result;

initial begin                                           clk=0;
    forever #10 clk = ~clk;
end


initial begin
    ena=0;
    forever @(negedgeclk) ena=~ena;
end

initial
begin
    rst=0;
    #10 rst=1;
    while (result<5) #20 $strobe("Counter value: %d", result);
    #100 rst=0;
    #10 rst=1;
    #100 $finish;
end
bin_cnttest_dev(clk, ena, rst, result);

endmodule