library ieee;
use ieee.std_logic_1164.all;

entity shiftregister is

port(
    load: in std_logic_vector(3 downto 0);
    input: in std_logic_vector(3 downto 0);
    output: out std_logic_vector(3 downto 0);
    q: out std_logic;
    ld: in std_logic;
    clr:in std_logic;
    clk:in std_logic
    );

    end entity shiftregister;


    Architecture shift of shiftregister is
    signal shift: std_logic_vector(3 downto 0);
    begin
    process(clk)
    begin
    if (clk'Event and CLK= '1') then
        if (clr='1') then --clear
            shift <= "0000";
        elsif(ld='1') then --load input from switches into shift register if load is asserted
            shift<= load;
        else
            shift <= input;
            shift <= '0' & shift(3 downto 1);-- concats a O to MSB and takes first 3 bits of of shift
            end if;
        end if;
    end process;
            q<=shift(0);-- Assigns LSB of shift to q
            output<=shift;
    end architecture shift;