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  1. ----------------------------------------------------------------------------------
  2. -- Company: Digilent Inc 2011
  3. -- Engineer: Michelle Yu
  4. -- Create Date: 17:18:24 08/23/2011
  5. --
  6. -- Module Name: Decoder - Behavioral
  7. -- Project Name: PmodKYPD
  8. -- Target Devices: Nexys3
  9. -- Tool versions: Xilinx ISE 13.2
  10. -- Description:
  11. -- This file defines a component Decoder for the demo project PmodKYPD.
  12. -- The Decoder scans each column by asserting a low to the pin corresponding to the column
  13. -- at 1KHz. After a column is asserted low, each row pin is checked.
  14. -- When a row pin is detected to be low, the key that was pressed could be determined.
  15. --
  16. -- Revision:
  17. -- Revision 0.01 - File Created
  18. ----------------------------------------------------------------------------------
  19. library IEEE;
  20. use IEEE.STD_LOGIC_1164.ALL;
  21. use IEEE.STD_LOGIC_ARITH.ALL;
  22. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  23.  
  24. entity Decoder is
  25. Port (
  26. clk : in STD_LOGIC;
  27. Row : in STD_LOGIC_VECTOR (3 downto 0);
  28. Col : out STD_LOGIC_VECTOR (3 downto 0);
  29. DecodeOut : out STD_LOGIC_VECTOR (3 downto 0));
  30. end Decoder;
  31.  
  32. architecture Behavioral of Decoder is
  33.  
  34. begin
  35.  
  36. end Behavioral;
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