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- ----------------------------------------------------------------------------------
- -- Company: Digilent Inc 2011
- -- Engineer: Michelle Yu
- -- Create Date: 17:18:24 08/23/2011
- --
- -- Module Name: Decoder - Behavioral
- -- Project Name: PmodKYPD
- -- Target Devices: Nexys3
- -- Tool versions: Xilinx ISE 13.2
- -- Description:
- -- This file defines a component Decoder for the demo project PmodKYPD.
- -- The Decoder scans each column by asserting a low to the pin corresponding to the column
- -- at 1KHz. After a column is asserted low, each row pin is checked.
- -- When a row pin is detected to be low, the key that was pressed could be determined.
- --
- -- Revision:
- -- Revision 0.01 - File Created
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- entity Decoder is
- Port (
- clk : in STD_LOGIC;
- Row : in STD_LOGIC_VECTOR (3 downto 0);
- Col : out STD_LOGIC_VECTOR (3 downto 0);
- DecodeOut : out STD_LOGIC_VECTOR (3 downto 0));
- end Decoder;
- architecture Behavioral of Decoder is
- begin
- end Behavioral;
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