`default_nettype none


module MagComp
#(parameter w = 3)
(input logic [w-1:0] A, B,
output logic AltB, AeqB, AgtB);
    assign AltB = (A < B) ? 1 : 0;
    assign AeqB = (A == B) ? 1 : 0;
    assign AgtB = (A > B) ? 1 : 0;
endmodule: MagComp

module Adder
#(parameter w = 3)
(input logic [w-1:0] A, B,
input logic Cin,
output logic [w-1:0] S,
output logic Cout);

    assign {Cout, S} = A + B + Cin;

endmodule: Adder

module multiplexer
#(parameter w = 3)
(input logic [w-1:0] I,
input logic [$clog2(w)-1:0] S,
output logic Y);

    assign Y = I[S];

endmodule: multiplexer

module mux2to1
#(parameter w = 3)
(input logic [w-1:0] I0,I1,
input logic S,
output logic [w-1:0] Y);

assign Y = (S==0)?I0:I1;

endmodule: mux2to1

module decoder
#(parameter w = 6)
(input logic [$clog2(w)-1:0] I, input logic en,
output logic [w - 1:0] D);
    always_comb begin
        D = 2'b0;
        if(en) begin
            D = 1'b1 << I;
        end
    end
endmodule: decoder


module ShiftReg_PISO_Right
#(parameter w = 8)
(output logic lowBit,
input logic [w-1:0] d,
input logic ld_L, sh_L,
input logic clock);
logic [w-1:0] q;
    assign lowBit = q[0];
    always_ff @(posedge clock)
        if (~ld_L)
            q <= d;
        else if (~sh_L)
        q <= q >> 1;
// SV shift operator fills
// with zeros
endmodule: ShiftReg_PISO_Right

module ShiftReg_SIPO_Left
#(parameter w = 8)
(input logic lowBit,
output logic [w-1:0] out,
input logic clock,en,clear);

    logic [w-1:0] q;
    assign q = {out[w-2:0],lowBit};
    register #(8) r(q,clock,en,clear,out);
endmodule: ShiftReg_SIPO_Left


module register
#(parameter w = 6)
(input logic [w-1:0] D,
input logic clock, en, clear,
output logic [w-1:0] Q);

    always_ff @(posedge clock) begin
        if (clear) Q <= 0;
        else if (en) Q <= D;
    end

endmodule: register