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- #include "msp.h"
- void ClockSetup(void);
- void BT_UART_PIN_SETUP(void);
- char testing = 'a';
- char testing123[11] = {'H', 'E', 'L', 'L', 'O', ' ', 'W', 'O', 'R', 'L', 'D'};
- int enumerator = 0;
- int main(void)
- {
- WDT_A->CTL = WDT_A_CTL_PW | // Stop watchdog timer
- WDT_A_CTL_HOLD;
- ClockSetup();
- BT_UART_PIN_SETUP();
- ClockSetup();
- // Enable global interrupt
- __enable_irq();
- //while (1){
- //EUSCI_A0->TXBUF = '0';
- //EUSCI_A1->TXBUF = '0';
- //EUSCI_A2->TXBUF = '0';
- //}
- }
- void BT_UART_PIN_SETUP(){ //enable pins for UART comm
- // Baud Rate calculation
- // 12000000/(16*9600) = 78.125
- // Fractional portion = 0.125
- // User's Guide Table 21-4: UCBRSx = 0x10
- // UCBRFx = int ( (78.125-78)*16) = 2
- P3->SEL0 |= (BIT3 + BIT2); // P3.2 RX
- P3->SEL1 &= ~(BIT3 + BIT3); // P3.3 TX
- // Configure UART
- EUSCI_A2->CTLW0 |= EUSCI_A_CTLW0_SWRST; // Put eUSCI in reset
- EUSCI_A2->CTLW0 = EUSCI_A_CTLW0_SWRST | // Remain eUSCI in reset
- EUSCI_B_CTLW0_SSEL__SMCLK; // Configure eUSCI clock source for SMCLK
- EUSCI_A2->BRW = 78; // 12000000/16/9600
- EUSCI_A2->MCTLW = (2 << EUSCI_A_MCTLW_BRF_OFS) |
- EUSCI_A_MCTLW_OS16;
- EUSCI_A2->CTLW0 &= ~EUSCI_A_CTLW0_SWRST; // Initialize eUSCI
- EUSCI_A2->IFG &= ~EUSCI_A_IFG_RXIFG; // Clear eUSCI RX interrupt flag
- EUSCI_A2->IE |= EUSCI_A_IE_RXIE; // Enable USCI_A1 RX interrupt
- // Enable eUSCIA1 interrupt in NVIC module
- NVIC->ISER[0] = 1 << ((EUSCIA2_IRQn) & 31);
- }
- // UART interrupt service routine
- void EUSCIA2_IRQHandler(){
- //EUSCI_A2->TXBUF = 'A';
- EUSCI_A2->TXBUF = testing123[enumerator % 11];
- enumerator = enumerator + 1;
- EUSCI_A2->IFG &= ~EUSCI_A_IFG_RXIFG;
- }
- void ClockSetup(void){
- CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
- CS->CTL0 = 0; // Reset tuning parameters
- CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz (nominal, center of 8-16MHz range)
- CS->CTL1 = CS_CTL1_SELA_2 | // Select ACLK = REFO
- CS_CTL1_SELS_3 | // SMCLK = DCO
- CS_CTL1_SELM_3; // MCLK = DCO
- CS->KEY = 0; // Lock CS module from unintended accesses
- }
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