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- module swfsj6(input [7:0]SW,
- input KEY1, KEY0, KEY2,
- output[6:0]HEX3, HEX2, HEX1, HEX0,
- output [9:0]LEDR);
- wire [7:0]sum;
- assign LEDR[7:0] = sum;
- add_sub_N_bits #(8) ex(SW[7:0],KEY2, KEY1, KEY0, sum, LEDR[9], LEDR[8]);
- decoder_hex_16 ex1(sum[7:4], HEX1);
- decoder_hex_16 ex2(sum[3:0], HEX0);
- decoder_hex_16 ex3(SW[7:4], HEX3);
- decoder_hex_16 ex4(SW[3:0], HEX2);
- endmodule
- module add_sub_N_bits
- #(N=8)
- (input [N-1:0] A,
- input add_sub,
- input clk,aclr,
- output reg [N-1:0] S,
- output reg overflow,carry);
- reg [N-1:0] B;
- always @(posedge clk, negedge aclr)
- if (!aclr) B <= {N{1'b0}};
- else B <= A;
- always @(posedge clk, negedge aclr)
- if (!aclr) {carry,S} <= {(N+1){1'b0}};
- else if (add_sub) {carry,S} <= S + B;
- else {carry,S} <= S - B;
- always @(posedge clk, negedge aclr)
- if (!aclr) overflow <= 1'b0;
- else overflow <= carry ^ S[N-1];
- endmodule
- module accumulator_N_bits_always
- #(N=8)
- (input [N-1:0] A,
- input clk,
- output reg [N-1:0] S,
- output reg overflow,carry);
- reg [N-1:0] B;
- always @(posedge clk)
- B <= A;
- always @(posedge clk)
- {carry,S} <= B + S;
- always @(posedge clk)
- overflow <= carry ^ S[N-1];
- endmodule
- module accumulator_N_bits_struct #(N=8)
- (input [N-1:0] A,
- input clk,
- output [N-1:0] S,
- output ov, ca);
- wire [N-1:0] B, C /* synthesis keep */;
- wire a, x /* synthesis keep */;
- register_N #(8) ex(A,clk,B);
- adder_N #(8) ex0(B,S,1'b0,C,a);
- register_N #(8) ex1(C,clk,S);
- FFD ex2(a,clk,ca);
- assign x = a ^ C[N-1];
- FFD ex3(x,clk,ov);
- endmodule
- module register_N
- #(N=8)
- (input [N-1:0] D,
- input clk,
- output reg [N-1:0] Q);
- always @(posedge clk)
- Q <= D;
- endmodule
- module adder_1_bits(
- input a,b,cin,
- output s,cout);
- assign s = a ^ b ^ cin;
- assign cout = a & b & (a ^ b) & cin;
- endmodule
- module adder_N
- #(parameter N=8)
- (input [N-1:0] A,B,
- input cin,
- output [N-1:0] S,
- output cout);
- assign {cout,S} = A + B + cin;
- endmodule
- module adder_ripple_carry_N_bits
- #(parameter N=4)
- (input [N-1:0] A, B, input CI,
- output [N-1:0] S, output CO);
- wire [N-1:0] c;
- generate
- genvar i;
- for (i=0; i<N; i=i+1)
- begin: ad
- case(i)
- 0: adder_1_bits x(A[i], B[i], CI, S[i], c[i]);
- N-1: adder_1_bits x(A[i], B[i], c[i-1], S[i], CO);
- default: adder_1_bits x(A[i], B[i], c[i-1], S[i], c[i]);
- endcase
- end
- endgenerate
- endmodule
- module FFD(input D, clk,
- output reg Q);
- always @(posedge clk)
- Q <= D;
- endmodule
- module decoder_hex_16(input [3:0]x, output reg [0:6]h);
- always @*
- case(x)
- 4'b0000: h = 7'b0000001;
- 4'b0001: h = 7'b1001111;
- 4'b0010: h = 7'b0010010;
- 4'b0011: h = 7'b0000110;
- 4'b0100: h = 7'b1001100;
- 4'b0101: h = 7'b0100100;
- 4'b0110: h = 7'b0100000;
- 4'b0111: h = 7'b0001111;
- 4'b1000: h = 7'b0000000;
- 4'b1001: h = 7'b0000100;
- 4'b1010: h = 7'b0001000;
- 4'b1011: h = 7'b1100000;
- 4'b1100: h = 7'b0011000;
- 4'b1101: h = 7'b1000010;
- 4'b1110: h = 7'b0110000;
- 4'b1111: h = 7'b0111000;
- endcase
- endmodule
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