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a guest Apr 25th, 2019 62 Never
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  1. module Verilog1(Out, A, B, Sel1, Sel0);
  2.     output reg [7: 0]Out;
  3.     input [7: 0]A;
  4.     input [7: 0]B;
  5.     input Sel1, Sel0;
  6.  
  7.     always @(Sel1 or Sel0 or A or B)
  8.         begin
  9.             case({Sel1, Sel0})                 
  10.             2'b00: Out = 0;
  11.             2'b01: Out = A+B;
  12.                 2'b10: Out = A-B;
  13.                 2'b11: Out = A*B;
  14.                 default: Out = 1'bx;           
  15.                 endcase
  16.         end
  17.         endmodule
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