//Brian Chan
//Jason Li
//Worked together with 4-member lab group (Helen Xu and Maria Mancz) in lab period

//IF
module IF (PC, instructions);
    input PC;
    input instructions;
    output instructreg;

    assign instructreg <= instructions[PC/4];
endmodule

//ID
module ID1(instruction, r1, r2, regwrite, wd);
    input instruction;
    output[5:0] opcode, funct;
    output[4:0] rs, rt, rd, shamt;
    wire[15:0] imm;
    output [31:0] imm2;
    output[25:0] addr;
    output branch_pcval;
    input[4:0] r1, r2; //read reg 1 + 2
    output[31:0] rd1, rd2; //read data 1 + 2
    input regwrite;
    input wd; //write data

    assign opcode <= instruction[30:25];

    if(opcode == 0)begin
        assign rs <= instruction[25:21];
        assign rt <= instruction[20:16];
        assign rd = instruction[15:11];
        assign shamt = instruction[10:6];
        assign funct = instruction[5:0];//R types
    end
    else begin
        assign rs <= instruction[25:21];
        assign rt <= instruction[20:16];
        assign imm <= instruction[15:0];
        //I types

    branch_pcval = instruction-imm;//if it is a branch instruction, calculate branch value
    end


    always @(posedge clk) begin
        rd1 = register[r1];
        rd2 = register[r2];
        if(imm[15] == 0) begin
            imm2 = imm;
        end
        else begin
            imm2 = [16'hFFFF, imm];
        end
        //if immediate is only 16 bits, extend to 32 bits
    end

    always @(*) begin
        if (regwrite) begin
            //change value in register if regwrite is 1
        end  //for write back
    end
  end

endmodule