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- //==================================================================================================
- // Filename : lab3.v
- // Created On : 2017-12-15 32:40:49
- // Last Modified : 2017-12-18 19:13:29
- // Revision :
- // Author : Ilya
- // Company : OKB RES SUAI
- // Email : tigoldghost@gmail.com
- //
- // Description :
- //
- //
- //==================================================================================================
- module lab3
- (
- input wire clk,
- input wire up,
- input wire down,
- output reg resultat
- );
- localparam st0 = 8'b0000_0001,
- st1 = 8'b0000_0010,
- st2 = 8'b0000_0100;
- localparam dr0 = 8'b0000_0001,
- dr1 = 8'b0000_0010,
- dr2 = 8'b0000_0100;
- localparam INC = 32'd15_000;
- localparam T = 32'd250_000;
- reg [15:0] cnt;
- reg signed [31:0] cnt2; // signed - знаковый регистр
- reg [7:0] state;
- reg [7:0]state_dr;
- reg signed [31:0] v;
- reg ra;
- reg rb;
- reg fl;
- reg signed [31:0] xu;
- assign in_up = ~up;
- assign in_down = ~down;
- initial begin
- cnt = 0; // 8'b_0000_0000;
- state = st0;
- v = T/32'd4;
- xu = 32'd0;
- state_dr = dr0;
- end
- //*************************************
- always @(posedge clk) begin
- case (state_dr)
- dr0: begin
- if (cnt > 16'd5) begin
- cnt = 0;
- if(in_up)state_dr = dr1;
- else if(in_down)state_dr = dr2;
- else state_dr = dr0;
- end
- else begin
- state_dr = dr0;
- end
- if (in_up||in_down) begin
- cnt = cnt +16'd1;
- end
- else begin
- cnt = 0;
- end
- end
- dr1:begin
- if(!in_up)begin
- if (cnt > 16'd5) begin
- state_dr = dr0;
- cnt = 0;
- ra = 1'b1;
- end
- else begin
- state_dr = dr1;
- end
- if (in_up == 1'b0) begin
- cnt = cnt + 16'd1;
- end
- else begin
- cnt = 0;
- end
- end
- else
- begin
- state_dr = dr1;
- end
- end
- dr2:begin
- if(!in_down)begin
- if (cnt > 16'd5) begin
- state_dr = dr0;
- cnt = 0;
- rb = 1'b1;
- end
- else begin
- state_dr = dr2;
- end
- if (in_down == 1'b0) begin
- cnt = cnt + 16'd1;
- end
- else begin
- cnt = 0;
- end
- end
- else
- begin
- state_dr = dr2;
- end
- end
- endcase
- case(state)
- st0:begin
- resultat = 1'b1;
- if (cnt2 > v) begin
- state = st1;
- cnt2 = 0;
- if (v <= INC-32'b1) begin
- v = 32'd0;
- xu = T;
- fl = 1'b1;
- end
- else if(v >= T) begin
- v = T ;
- xu = 32'd1;
- end
- else begin
- xu = T - v;
- end
- end
- else begin
- state = st0;
- cnt2 = cnt2 + 32'd1;
- end
- end
- st1:begin
- resultat = 1'b0;
- if (cnt2 > xu) begin // T = 200
- state = st2;
- cnt2 = 0;
- end
- else begin
- state = st1;
- cnt2 = cnt2 + 32'd1;
- end
- end
- st2:begin
- if (ra) begin
- v = v + INC;
- fl = 1'b0;
- end
- if (rb && !fl) begin
- v = v - INC;
- end
- state = st0;
- ra = 1'b0;
- rb = 1'b0;
- end
- endcase
- end
- endmodule
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