Code_ATM

library IEEE;
use IEEE.std_logic_1164.all;
entity lab7 is
port (
	SW0 : in STD_LOGIC; --active low set input
	SW1 : in STD_LOGIC; --active low reset input
	LEDR0 : buffer STD_LOGIC; --data output
	LEDR1 : buffer STD_LOGIC --inverted data output
);
end lab7;
architecture lab7_arch of lab7 is
begin
	LEDR0 <= NOT(SW0 or LEDR1); --cross-coupled NAND gates
	LEDR1 <= NOT(SW1 or LEDR0);
end lab7_arch;