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- // File: vga_timing.v
- // This is the vga timing design for EE178 Lab #4.
- // The `timescale directive specifies what the
- // simulation time units are (1 ns here) and what
- // the simulator time step should be (1 ps here).
- `timescale 1 ns / 1 ps
- // Declare the module and its ports. This is
- // using Verilog-2001 syntax.
- module vga_timing (
- output reg [10:0] vcount, //zmiana na reg
- output reg vsync,
- output reg vblnk,
- output reg [10:0] hcount,
- output reg hsync,
- output reg hblnk,
- input wire pclk
- );
- reg vsync_nxt = 0;
- reg vblnk_nxt = 0;
- reg hsync_nxt = 0;
- reg hblnk_nxt = 0;
- reg [10:0] vcount_nxt = 0;
- reg [10:0] hcount_nxt = 0;
- always@(posedge pclk)
- begin
- vcount <= vcount_nxt;
- hcount <= hcount_nxt;
- vblnk <= vblnk_nxt;
- vsync <= vsync_nxt;
- hblnk <= hblnk_nxt;
- hsync <= hsync_nxt;
- end
- always @(*)
- begin
- if(hcount < 1055)
- begin
- hcount_nxt = hcount + 1;
- vcount_nxt = vcount;
- end
- else
- begin
- hcount_nxt = 0;
- if(vcount < 628)
- vcount_nxt = vcount + 1;
- else
- vcount_nxt = 0;
- end
- vblnk_nxt = (vcount_nxt >= 600);
- vsync_nxt = (vcount_nxt >= 601 && vcount_nxt <= 605);
- hblnk_nxt = (hcount_nxt >= 800);
- hsync_nxt = (hcount_nxt >= 840 && hcount_nxt <= 968);
- end
- /*
- assign vblnk_nxt = (vcount_nxt >= 600);
- assign vsync_nxt = (vcount_nxt >= 601 && vcount_nxt <= 605);
- assign hblnk_nxt = (hcount_nxt >= 800);
- assign hsync_nxt = (hcount_nxt >= 840 && hcount_nxt <= 968);
- */
- // Describe the actual circuit for the assignment.
- // Video timing controller set for 800x600@60fps
- // using a 40 MHz pixel clock per VESA spec.
- endmodule
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