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Axoloti 23LC1024 delay test object

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  1. <axoObjectPatcherObject id="patch/object" uuid="e37e7f23-530e-4e58-964a-2727988daf44">
  2.    <inlets>
  3.       <frac32buffer name="in1" description="wave input"/>
  4.    </inlets>
  5.    <outlets>
  6.       <frac32buffer name="out1" description="delayed output"/>
  7.    </outlets>
  8.    <displays>
  9.       <int32.hexlabel name="mode"/>
  10.       <int32.hexlabel name="sendAddr"/>
  11.       <frac32.s.chart name="sendData"/>
  12.       <int32.hexlabel name="receiveAddr"/>
  13.       <frac32.s.chart name="receiveData"/>
  14.    </displays>
  15.    <params/>
  16.    <attribs/>
  17.    <includes/>
  18.    <code.declaration><![CDATA[// SRAM Instructions
  19. #define RDMR  0x05
  20. #define WRMR  0x01
  21. #define WRITE 0x02
  22. #define READ  0x03
  23.  
  24. // SRAM modes
  25. #define BYTE_MODE       0x00
  26. #define PAGE_MODE       0x80
  27. #define SEQUENTIAL_MODE 0x40
  28.  
  29. // 23lc1024 SRAM address is 17bits long
  30. static const uint32_t LENGTHMASK = 0x1FFFF;
  31.  
  32. uint8_t *txbuf;
  33. uint8_t *rxbuf;
  34.  
  35. uint32_t writeAddress = 0;
  36. uint32_t readAddress = 0;
  37.  
  38. ////////////////////////////////////////////////////////////////////////////////
  39.  
  40. void setMode(uint8_t mode)
  41. {
  42.     txbuf[0] = WRMR;
  43.     txbuf[1] = mode;
  44.    
  45.     spiSelect(&SPID1);
  46.     //write WRMR instruction, write mode byte
  47.     spiSend(&SPID1, 2, txbuf);
  48.  
  49.     spiUnselect(&SPID1);
  50. }
  51.  
  52.  
  53. uint8_t getMode(void)
  54. {
  55.     txbuf[0] = RDMR;
  56.  
  57.     spiSelect(&SPID1);
  58.     //write RDMR instruction
  59.     spiSend(&SPID1, 1, txbuf);
  60.     //receive MODE info
  61.     spiReceive(&SPID1, 1, &rxbuf[0]);
  62.     spiUnselect(&SPID1);
  63.  
  64.     return rxbuf[0];
  65. }
  66.  
  67.  
  68. uint8_t writeByte(uint8_t data, uint32_t address)
  69. {
  70.     // put together tx buffer:
  71.     // WRITE instruction
  72.     txbuf[0] = WRITE;
  73.     // 17bit address to write to
  74.     txbuf[1] = (address>>16) & 0x01;
  75.     txbuf[2] = address>>8;
  76.     txbuf[3] = address;
  77.     // data byte to be written
  78.     txbuf[4] = data;
  79.  
  80.     // CS low
  81.     spiSelect(&SPID1);
  82.  
  83.     // send WRITE byte, 3-byte address, data byte
  84.     spiSend(&SPID1, 5, txbuf); //write byte, 3-byte address, data byte
  85.  
  86.     // CS high
  87.     spiUnselect(&SPID1);
  88.  
  89.     return 0; // TODO: add error check
  90. }
  91.  
  92.  
  93. uint8_t readByte(uint32_t address)
  94. {
  95.     // put together tx buffer to send reading instructions:
  96.     // READ instruction
  97.     txbuf[0] = READ;
  98.     // 17bit address to read from
  99.     txbuf[1] = (address>>16) % 0x01;
  100.     txbuf[2] = address>>8;
  101.     txbuf[3] = address;
  102.  
  103.     // CS low
  104.     spiSelect(&SPID1);
  105.  
  106.     // send READ byte, 3-byte address
  107.     spiSend(&SPID1, 4, txbuf); // send request to read back ram address 0
  108.     // receive data byte
  109.     spiReceive(&SPID1, 1, rxbuf); // receive byte in SRAM
  110.  
  111.     // CS high
  112.     spiUnselect(&SPID1);
  113.  
  114.     // return byte read
  115.     return rxbuf[0];
  116. }
  117.  
  118.  
  119. uint16_t writeShort(uint16_t data, uint32_t address)
  120. {
  121.     // put together tx buffer:
  122.     // WRITE instruction
  123.     txbuf[0] = WRITE;
  124.     // 17bit address to write to
  125.     txbuf[1] = (address>>16) & 0x01;
  126.     txbuf[2] = address>>8;
  127.     txbuf[3] = address;
  128.     // data byte to be written
  129.     txbuf[4] = data>>8; //high byte
  130.     txbuf[5] = data; // low byte
  131.  
  132.     // CS low
  133.     spiSelect(&SPID1);
  134.  
  135.     // send WRITE byte, 3-byte address, two data bytes
  136.     spiSend(&SPID1, 6, txbuf);
  137.  
  138.     // CS high
  139.     spiUnselect(&SPID1);
  140.  
  141.     return 0; // TODO: add error check?
  142. }
  143.  
  144.  
  145. uint16_t readShort(uint32_t address)
  146. {
  147.     // put together tx buffer to send reading command:
  148.     // READ instruction
  149.     txbuf[0] = READ;
  150.     // 17bit address to read from
  151.     txbuf[1] = (address>>16) % 0x01;
  152.     txbuf[2] = address>>8;
  153.     txbuf[3] = address;
  154.  
  155.     // CS low
  156.     spiSelect(&SPID1);
  157.  
  158.     // send READ byte, 3-byte address
  159.     spiSend(&SPID1, 4, txbuf);
  160.     // receive data byte
  161.     spiReceive(&SPID1, 2, rxbuf); // receive two bytes from SRAM
  162.  
  163.     // CS high
  164.     spiUnselect(&SPID1);
  165.  
  166.     // return uint16 read
  167.     return (rxbuf[0]<<8 | rxbuf[1]); // high byte, low byte
  168. }]]></code.declaration>
  169.    <code.init><![CDATA[static uint8_t _txbuf[8] __attribute__ ((section (".sram2")));
  170. static uint8_t _rxbuf[8] __attribute__ ((section (".sram2")));
  171.  
  172. txbuf = _txbuf;
  173. txbuf = _txbuf;
  174.  
  175. // valid SRAM modes:
  176. // BYTE_MODE       0x00
  177. // PAGE_MODE       0x80
  178. // SEQUENTIAL_MODE 0x40
  179.  
  180. //set transfer mode to SEQUENTIAL_MODE (default anyway)
  181. setMode(SEQUENTIAL_MODE);
  182.  
  183. // read MODE register and display active mode (should be 0x00, 0x80, or 0x40)
  184. disp_mode = getMode();
  185.  
  186.  
  187. // (dirty) zero out entire 23LC1024 SRAM
  188. for (int i=0; i<LENGTHMASK; i++)
  189. {
  190.     writeShort(0, i);
  191. }]]></code.init>
  192.    <code.srate><![CDATA[// SRAM Instructions:
  193. // RDMR  0x05
  194. // WRMR  0x01
  195. // WRITE 0x02
  196. // READ  0x03
  197.  
  198.     // send uint32 to SRAM
  199.     writeShort(inlet_in1>>21, writeAddress);
  200.  
  201.     // display writeAddress (3 bytes) and tx buffer (2 bytes) in patcher
  202.     disp_sendAddr = writeAddress;
  203.     disp_sendData = inlet_in1;
  204.  
  205.     // readAddress reads one int16_t sample ahead, i.e. the oldest sample in
  206.     // the delay line, right before its memory location gets overwritten
  207.     // with the newest sample. Wrap read address.
  208.     readAddress = (writeAddress + sizeof(int16_t)) & LENGTHMASK;
  209.    
  210.     // receive int16 from SRAM
  211.     outlet_out1 =  (readShort(readAddress))<<21;
  212.  
  213.     // display readAddress (24bits) followed by rx buffer (8bits) in patcher
  214.     disp_receiveAddr = readAddress;
  215.     disp_receiveData = outlet_out1; //= (rxbuf[0]<<8 | rxbuf[1])<<11;
  216.  
  217.     // increment and wrap write address
  218.     writeAddress = (writeAddress + sizeof(int16_t)) & LENGTHMASK;]]></code.srate>
  219. </axoObjectPatcherObject>
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