----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:22:35 03/22/2018
-- Design Name:
-- Module Name:    RAM
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RAM is
    Port ( read_adr : in  STD_LOGIC_VECTOR (9 downto 0);
           write_adr : in  STD_LOGIC_VECTOR (9 downto 0);
           CLK_50 : in  STD_LOGIC;
           input_data : in  STD_LOGIC_VECTOR (8 downto 0);
           output_data : out  STD_LOGIC_VECTOR (8 downto 0);
           write_enable : in  STD_LOGIC);
end RAM;

architecture Behavioral of RAM is
type ram_type is array (0 to 799) of std_logic_vector (8 downto 0);
signal RAM: ram_type;
begin
process (CLK_50)
begin
   if (CLK_50'event and CLK_50 = '1') then
      if (write_enable = '1') then
         RAM(conv_integer(write_adr)) <= input_data;
      end if;
      output_data <= RAM(conv_integer(read_adr));
   end if;
end process;


end Behavioral;