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alpha_lights

grzemot Jun 19th, 2019 (edited) 89 Never
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  1. //////////////////////////////////////////////////////////////////////////////////
  2. //
  3. // Link:https://imgur.com/a/g6oK4vi
  4. //
  5. // Create Date: 18.06.2019 08:35:02
  6. // Design Name:
  7. // Module Name: Alpha_lights
  8. // Project Name:
  9. // Target Devices:
  10. // Tool Versions:
  11. // Description:
  12. //
  13. // Dependencies:
  14. //
  15. // Revision:
  16. // Revision 0.01 - File Created
  17. // Additional Comments:
  18. //
  19. //////////////////////////////////////////////////////////////////////////////////
  20.  
  21.  
  22. module Alpha_lights(alpha, beta, gamma, alpha_cond, beta_cond, clk, rst);
  23. parameter   A=3'b001,
  24.             AB=3'b011,
  25.             B=3'b010,
  26.             BC=3'b110,
  27.             C=3'b100,
  28.             CA=3'b101;
  29.            
  30. input  clk, rst;
  31. output reg[2:0] alpha ,beta , gamma;
  32. output reg alpha_cond , beta_cond;
  33.  
  34. reg[7:0] cnt=0;
  35. reg cnt10s=0, cnt3s=0, cnt_en=0;
  36.  
  37. reg[2:0] state, next_state;
  38.  
  39.  
  40. always @(posedge clk or negedge rst) //  rst
  41. begin
  42.  
  43.     if(~rst) state <= A;
  44.     else if(cnt_en == 1) state <= next_state;
  45.  
  46. end
  47. always @(posedge clk) // clk
  48. begin
  49.  
  50.    if(cnt_en == 0)
  51.    begin
  52.    cnt <= cnt + 1;
  53.     if (cnt3s&&(cnt == 3))
  54.         begin
  55.         cnt_en = 1;
  56.         cnt <= 0;
  57.         //state  <= next_state;
  58.         end
  59.     if(cnt10s&&(cnt==15))
  60.         begin
  61.         cnt_en = 1;
  62.         cnt <= 0;
  63.         //state  <= next_state;
  64.         end
  65.    end
  66.    else
  67.    begin
  68.     cnt_en = 0;
  69.     cnt <= cnt + 1;
  70.    end
  71.  end
  72.  
  73. always @(posedge clk)
  74. begin
  75.     case(state)
  76.     A:
  77.     begin
  78.     alpha = 3'b001;
  79.     beta = 3'b100;
  80.     gamma = 3'b100;
  81.     alpha_cond = 0;
  82.     beta_cond = 1;
  83.    
  84.     cnt10s = 1;
  85.     cnt3s = 0;
  86.     if(cnt_en)
  87.     begin
  88.     next_state = AB;
  89.    
  90.     end  
  91.     else  next_state = A;
  92.     end
  93.     AB:
  94.     begin
  95.        alpha = 3'b010;
  96.        beta =  3'b100;
  97.        gamma = 3'b100;
  98.        alpha_cond = 0;
  99.        beta_cond = 0;
  100.        
  101.        cnt10s = 0;
  102.        cnt3s = 1;
  103.        
  104.        next_state = B;
  105.     end
  106.     B:
  107.     begin
  108.        alpha = 3'b100;
  109.        beta =  3'b001;
  110.        gamma = 3'b100;
  111.        alpha_cond = 1;
  112.        beta_cond = 0;
  113.        
  114.         cnt10s = 1;
  115.         cnt3s = 0;
  116.         next_state = BC;
  117.        
  118.     end
  119.     BC:
  120.      begin
  121.         alpha = 3'b100;
  122.         beta =  3'b010;
  123.         gamma = 3'b100;
  124.         alpha_cond = 0;
  125.         beta_cond = 0;
  126.        
  127.        cnt10s = 0;
  128.        cnt3s = 1;
  129.        next_state = C;
  130.      end
  131.     C:
  132.      begin
  133.         alpha = 3'b100;
  134.         beta =  3'b100;
  135.         gamma = 3'b001;
  136.         alpha_cond = 0;
  137.         beta_cond = 1;
  138.        
  139.         cnt10s = 1;
  140.         cnt3s = 0;
  141.         next_state = CA;
  142.      end
  143.     CA:
  144.      begin
  145.         alpha = 3'b100;
  146.         beta =  3'b100;
  147.         gamma = 3'b010;
  148.         alpha_cond = 0;
  149.         beta_cond = 0;
  150.        
  151.        cnt10s = 0;
  152.        cnt3s = 1;
  153.        next_state = A;
  154.      end
  155.     default: next_state = A;
  156.     endcase
  157. end
  158. endmodule
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