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tb_display7

DomMisterSoja Apr 9th, 2018 (edited) 73 Never
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  1. library ieee;                                                         --biblioteca utilizada: ieee
  2. use ieee.std_logic_1164.all;                                          --inclui todo o pacote padrão 1164
  3. use ieee.numeric_std.all;
  4.  
  5. entity tb_display7 is
  6. end entity;
  7.  
  8. architecture arch of tb_display7 is
  9.  
  10. component display7 is                                                   --inicio da declaração da entidade
  11.   port( clk, rst : in std_logic;
  12.     in3, in2, in1, in0 : std_logic_vector(3 downto 0);
  13.     an : out std_logic_vector(3 downto 0);
  14.     sseg : out std_logic_vector (7 downto 0)
  15. );
  16.  
  17. end component;  
  18.  
  19.     signal clk, rst :  std_logic;
  20.     signal in3, in2, in1, in0 : std_logic_vector(3 downto 0);
  21.     signal an :  std_logic_vector(3 downto 0);
  22.     signal sseg :  std_logic_vector (7 downto 0);
  23. begin
  24. dut: display7 port map (clk, rst, in3, in2, in1, in0, an, sseg);
  25.  
  26. process
  27. begin
  28.  
  29. clk <= '0';
  30. wait for 10ns;
  31. clk <= '1';
  32. wait for 10ns;
  33. end process;
  34.  
  35. process
  36. begin
  37.  
  38. rst <= '1';
  39. wait for 10ns;
  40. rst <= '0';
  41. wait;
  42. end process;
  43.  
  44. process
  45. begin
  46.  
  47. in3 <= "0000";
  48. in2 <="0000";
  49. in1 <= "0000";
  50. in0 <="0000";
  51.  
  52.  
  53. in3 <= "0100";
  54. wait for 30ns;
  55. in2 <="0111";
  56. wait for 30ns;
  57. in1 <= "0101";
  58. wait for 30ns;
  59. in0 <="1001";
  60. wait;
  61. end process;
  62.  
  63. end arch;
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