architecture arch of cpu_ctrl is
    signal in_data: std_logic_vector(7 downto 0);
    signal out_data: std_logic_vector(7 downto 0);
    signal buf_ce_n: std_logic;
    signal buf_we_n: std_logic;
    signal buf_oe_n: std_logic;

    signal npc: std_logic_vector(15 downto 0); -- Next PC
    signal state: std_logic_vector(3 downto 0);

    signal opcode: std_logic_vector(15 downto 0);
    constant STATE_FETCH1: std_logic_vector(3 downto 0) := "0000";
    constant STATE_FETCH2: std_logic_vector(3 downto 0) := "0001";
    constant STATE_DECODE: std_logic_vector(3 downto 0) := "0010";
begin
    ce_n <= buf_ce_n;
    we_n <= buf_we_n;
    oe_n <= buf_oe_n;

    process(clk, ready_n, reset_n)
    begin
        if(rising_edge(clk)) then
            if(reset_n = '0') then
                addr <= (others => '1');
                buf_ce_n <= '1';
                buf_oe_n <= '1';
                buf_we_n <= '1';
                state <= STATE_FETCH1; -- Reset the current state
            else
                if(ready_n = '0') then
                    case state is
                        when STATE_FETCH1 =>
                            pc <= "ZZZZZZZZZZZZZZZZ";
                            addr <= pc;
                            buf_ce_n <= '0';
                            buf_oe_n <= '0';
                            buf_we_n <= '1';
                            state <= STATE_FETCH2;

                        when STATE_FETCH2 =>
                            pc <= "ZZZZZZZZZZZZZZZZ";
                            addr <= pc + 1;
                            npc <= pc + 2;
                            buf_ce_n <= '0';
                            buf_oe_n <= '0';
                            buf_we_n <= '1';
                            data <= "ZZZZZZZZ";
                            opcode(15 downto 8) <= data;
                            state <= STATE_DECODE;

                        when STATE_DECODE =>
                            pc <= npc;
                            pc <= "ZZZZZZZZZZZZZZZZ";
                            buf_ce_n <= '1';
                            buf_oe_n <= '1';
                            buf_we_n <= '1';
                            data <= "ZZZZZZZZ";
                            opcode(7 downto 0) <= data;
                            state <= "1000";

                        when others =>
                            addr <= opcode;
                            buf_ce_n <= '1';
                            buf_oe_n <= '1';
                            buf_we_n <= '1';
                    end case;
                end if;
            end if;
        end if;
    end process;

    process(ready_n, buf_ce_n, buf_we_n, buf_oe_n)
    begin
        if(ready_n = '0') then
            if(buf_ce_n = '0') then
                if(buf_we_n = '0') then
                    data <= out_data;
                elsif(buf_oe_n = '0') then
                    data <= "ZZZZZZZZ";
                    in_data <= data;
                end if;
            end if;
        end if;
    end process;

end;