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Ankur Patel

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Apr 7th, 2014
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  1. diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
  2. index 21cac7b..769ec4d 100644
  3. --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
  4. +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
  5. @@ -30,6 +30,60 @@
  6.  
  7.  #include "mxs_init.h"
  8.  
  9. +/* Enable the following if you only have a VDD5V source only and no DCDC_BATT
  10. + * source.  This includes configurations with and without a supercap on the
  11. + * BATTERY pin as  * shown in the i.MX28 reference schematic (applies to
  12. + * i.MX233 as well).
  13. + *
  14. + * NOTE: If both a DCDC_BATT and VDD5V source are present, this is not meant to
  15. + * select which one to use.  This is only for hardware configurations this no
  16. + * DCDC_BATT power source.
  17. +*/
  18. +#define NO_DCDC_BATT_SOURCE
  19. +
  20. +/* Enable the following if you only have a DCDC_BATT source only and no V
  21. + * This includes configurations with and without a supercap on the BATTERY pin as
  22. + * shown in the i.MX28 reference schematic (applies to i.MX233 as well).
  23. + *
  24. + * NOTE: If both a DCDC_BATT and VDD5V source are present, this is not meant to
  25. + * select which one to use.  This is only for hardware configurations this no
  26. + * VDD5V power source.
  27. +*/
  28. +//#define NO_VDD5V_SOURCE
  29. +
  30. +
  31. +/* We need to protect the DCDC from trying to source charge
  32. + * from too low of a voltage.  This limit is given in
  33. + * the characteristics and specifications section of the
  34. + * reference manual for i.MX233 and in the datasheet
  35. + * for i.MX28x.  Also, we want to stop sourcing
  36. + * charge from the battery before the battery's internal
  37. + * protection circuitry may activate which would then cause
  38. + * us to lose RTC time.  By default, we will use 3.0V as the
  39. + * battery's maximum voltage that may cause it's undervoltage protection
  40. + * circuitry to activate.
  41. + */
  42. +#ifdef CONFIG_MX28
  43. +/*
  44. + * The minimum DCDC operating voltage for i.MX28 with loading is 3.3V.
  45. + * we will set the BRWNOUT_LVL bitfield the 3.2V value for 0.1V margin.
  46. + */
  47. +#define BATTERY_BRWNOUT_BITFIELD_VALUE 20 /* 20 = 3.2V */
  48. +#else
  49. +/*
  50. + * At the time of this writing,
  51. + * 3V is greater than the minimum DCDC operating voltage for i.MX233
  52. + * as listed in by the "Battery / DCDC Input Voltage" parameter listed
  53. + * in the reference manual so we will set the BRWNOUT_LVL bitfield to 3V value.
  54. + */
  55. +#define BATTERY_BRWNOUT_BITFIELD_VALUE 15 /* 15 = 3.0V */
  56. +#endif
  57. +
  58. +/* if you accidentally define both, don't allow a successful compile. */
  59. +#if defined(NO_DCDC_BATT_SOURCE) && defined(NO_VDD5V_SOURCE)
  60. +#error Invalid power source configuration.
  61. +#endif
  62. +
  63.  static void mxs_power_clock2xtal(void)
  64.  {
  65.         struct mxs_clkctrl_regs *clkctrl_regs =
  66. @@ -48,8 +102,13 @@ static void mxs_power_clock2pll(void)
  67.         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
  68.                         CLKCTRL_PLL0CTRL0_POWER);
  69.         early_delay(100);
  70. +      
  71. +      
  72.         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
  73.                         CLKCTRL_CLKSEQ_BYPASS_CPU);
  74. +      
  75. +       //clrbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
  76. +       //              CLKCTRL_CLKSEQ_BYPASS_CPU);
  77.  }
  78.  
  79.  static void mxs_power_clear_auto_restart(void)
  80. @@ -64,7 +123,7 @@ static void mxs_power_clear_auto_restart(void)
  81.         writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
  82.         while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
  83.                 ;
  84. -
  85. +       #if 0
  86.         /*
  87.          * Due to the hardware design bug of mx28 EVK-A
  88.          * we need to set the AUTO_RESTART bit.
  89. @@ -83,6 +142,7 @@ static void mxs_power_clear_auto_restart(void)
  90.                 ;
  91.         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
  92.                 ;
  93. +       #endif
  94.  }
  95.  
  96.  static void mxs_power_set_linreg(void)
  97. @@ -217,11 +277,18 @@ static void mxs_power_init_4p2_params(void)
  98.                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
  99.                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
  100.  
  101. +#ifdef NO_DCDC_BATT_SOURCE
  102. +/* don't use the DCDC_BATT source if configured not to */
  103. +       clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  104. +               POWER_DCDC4P2_DROPOUT_CTRL_MASK,
  105. +               POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
  106. +#else
  107.         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  108.                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
  109.                 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
  110.                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
  111. -
  112. +#endif
  113. +      
  114.         clrsetbits_le32(&power_regs->hw_power_5vctrl,
  115.                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  116.                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  117. @@ -376,7 +443,20 @@ static void mxs_power_init_4p2_regulator(void)
  118.                         POWER_DCDC4P2_BO_MASK,
  119.                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
  120.  
  121. -       if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
  122. +       tmp = (readl(&power_regs->hw_power_5vctrl) &
  123. +               POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
  124. +               POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
  125. +       while (tmp < 0x3f) {
  126. +                       tmp++;
  127. +                       tmp2 = readl(&power_regs->hw_power_5vctrl);
  128. +                       tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
  129. +                       tmp2 |= tmp <<
  130. +                               POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
  131. +                       writel(tmp2, &power_regs->hw_power_5vctrl);
  132. +                       early_delay(100);
  133. +       }
  134. +
  135. +/*     if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
  136.                 setbits_le32(&power_regs->hw_power_5vctrl,
  137.                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  138.         } else {
  139. @@ -402,7 +482,7 @@ static void mxs_power_init_4p2_regulator(void)
  140.                         }
  141.                 }
  142.         }
  143. -
  144. +*/
  145.         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
  146.         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  147.  }
  148. @@ -412,11 +492,11 @@ static void mxs_power_init_dcdc_4p2_source(void)
  149.         struct mxs_power_regs *power_regs =
  150.                 (struct mxs_power_regs *)MXS_POWER_BASE;
  151.  
  152. -       if (!(readl(&power_regs->hw_power_dcdc4p2) &
  153. +       /*if (!(readl(&power_regs->hw_power_dcdc4p2) &
  154.                 POWER_DCDC4P2_ENABLE_DCDC)) {
  155.                 hang();
  156. -       }
  157. -
  158. +       }*/
  159. +       debug_printf("mxs_power_init_dcdc_4p2_source \r\n");
  160.         mxs_enable_4p2_dcdc_input(1);
  161.  
  162.         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
  163. @@ -631,7 +711,7 @@ static void mxs_init_batt_bo(void)
  164.         /* Brownout at 3V */
  165.         clrsetbits_le32(&power_regs->hw_power_battmonitor,
  166.                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
  167. -               15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
  168. +               BATTERY_BRWNOUT_BITFIELD_VALUE << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
  169.  
  170.         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  171.         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
  172. @@ -654,6 +734,8 @@ static void mxs_switch_vddd_to_dcdc_source(void)
  173.  static void mxs_power_configure_power_source(void)
  174.  {
  175.         int batt_ready, batt_good;
  176. +       struct mxs_rtc_regs *rtc_regs =
  177. +               (struct mxs_rtc_regs *)MXS_RTC_BASE;
  178.         struct mxs_power_regs *power_regs =
  179.                 (struct mxs_power_regs *)MXS_POWER_BASE;
  180.         struct mxs_lradc_regs *lradc_regs =
  181. @@ -661,6 +743,58 @@ static void mxs_power_configure_power_source(void)
  182.  
  183.         mxs_src_power_init();
  184.  
  185. +#ifdef  NO_DCDC_BATT_SOURCE
  186. +       /* device configured for no source to DCDC_BATT input (5V only power
  187. +        * source).  This boot option doesn't waste time looking for a good
  188. +        *  battery.  Battery powered operation and automatic voltage
  189. +        *  measurements are disabled.
  190. +       */
  191. +    // bit 11 of PERSISTENT1
  192. +       setbits_le32(&rtc_regs->hw_rtc_persistent1,     RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER);
  193. +
  194. +    debug_printf("\r\nConfigured for 5v only power source.\
  195. +               Battery powered operation disabled.\r\n");
  196. +      
  197. +       /* Disable automatic battery voltage measurements which seem unnecessary
  198. +        * for this configuration.
  199. +        */
  200. +    setbits_le32(&power_regs->hw_power_battmonitor,    POWER_BATTMONITOR_EN_BATADJ);
  201. +    writel(LRADC_CONVERSION_AUTOMATIC, &lradc_regs->hw_lradc_conversion_clr);
  202. +    writel(525 << POWER_BATTMONITOR_BATT_VAL_OFFSET, &power_regs->hw_power_battmonitor);
  203. +
  204. +
  205. +       clrsetbits_le32(&power_regs->hw_power_battmonitor,
  206. +               POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
  207. +               BATTERY_BRWNOUT_BITFIELD_VALUE << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
  208. +
  209. +       mxs_5v_boot();
  210. +
  211. +//#ifndef MXS_VBUS_CURRENT_DRAW
  212. +       mxs_power_clock2pll();
  213. +//#endif
  214. +
  215. +#elif defined(NO_VDD5V_SOURCE)
  216. +       printf("\r\nConfigured for DCDC_BATT only power source.\r\n");
  217. +
  218. +#ifdef CONFIG_MX28
  219. +       /* We only care about the DCDC_BATT source in this configuration */
  220. +       setbits_le32(&power_regs->hw_power_battmonitor,
  221. +                       POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN);
  222. +#endif
  223. +
  224. +       clrbits_le32(&rtc_regs->hw_rtc_persistent1,     RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER);
  225. +
  226. +       mxs_batt_boot();
  227. +       mxs_power_clock2pll();
  228. +      
  229. +       mxs_init_batt_bo();
  230. +
  231. +       /* Configured to not use a VDD5V source */
  232. +       setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ILIMIT_EQ_ZERO);
  233. +#else
  234. +
  235. +       clrbits_le32(&rtc_regs->hw_rtc_persistent1,     RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER);
  236. +
  237.         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  238.                 batt_ready = mxs_is_batt_ready();
  239.                 if (batt_ready) {
  240. @@ -686,6 +820,8 @@ static void mxs_power_configure_power_source(void)
  241.  
  242.         mxs_init_batt_bo();
  243.  
  244. +#endif /* #ifdef NO_DCDC_BATT_SOURCE */
  245. +
  246.         mxs_switch_vddd_to_dcdc_source();
  247.  
  248.  #ifdef CONFIG_MX23
  249. @@ -937,9 +1073,9 @@ void mxs_power_init(void)
  250.         mxs_enable_output_rail_protection();
  251.  
  252.         mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
  253. -       mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
  254. +       mxs_power_set_vddx(&mxs_vddd_cfg, 1350, 1200);
  255.  #ifdef CONFIG_MX23
  256. -       mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
  257. +       mxs_power_set_vddx(&mxs_vddmem_cfg, 3300, 3150);
  258.  #endif
  259.         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
  260.                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
  261. @@ -948,6 +1084,18 @@ void mxs_power_init(void)
  262.  
  263.         writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
  264.  
  265. +#if defined(NO_DCDC_BATT_SOURCE) && defined(CONFIG_MX28)
  266. +       /* On i.MX28, a new bit has been added to allow automatic hardware
  267. +        * shutdown if VDD4P2 browns out.  If we permanently only have a VDD5V
  268. +        * source, we want to enable this bit.  For devices with dead batteries,
  269. +        * we could also temporarily set this bit until the kernel battery
  270. +        * charger sufficiently charges the battery but we won't do this for
  271. +        * now as the latest release kernel versions aren't aware of  it
  272. +        * and thus don't handle the proper setting/clearing of this bit.
  273. +        */
  274. +       writel(1<<7, &power_regs->hw_power_refctrl);
  275. +#endif
  276. +
  277.         early_delay(1000);
  278.  }
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