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  1. ** licznik 74160 3 do 5 **
  2. *
  3. * NI Multisim to SPICE Netlist Export
  4. * Generated by: oskar
  5. * Mon, Oct 21, 2019 21:01:57
  6. *
  7.  
  8. *## Multisim Component U3 ##*
  9. aU3_A [dU3.1A dU3.1B]
  10. + [dU3.1Y] 74LS386__74STD__1
  11.  
  12. xU3_A.1A 1 dU3.1A VCC GND TTL_RCV__NON__1
  13.  
  14.  
  15. xU3_A.1B 3 dU3.1B VCC GND TTL_RCV__NON__1
  16.  
  17.  
  18. xU3_A.1Y dU3.1Y 4 VCC GND TTL_DRV__NON__1
  19.  
  20.  
  21. *## Multisim Component X7 ##*
  22. * !!!BEGIN-INTERACT
  23. * : v_level ++++f2 ;
  24. * 0.0 VARIABLE r1Volt
  25. * 0.0 VARIABLE r1Cur
  26. *
  27. * :UPDATE_SETTINGS
  28. * 1 5 0 SET_SUBCOMP_PRP
  29. * 0 7 0 SET_SUBCOMP_PRP
  30. * 0 8 0 SET_SUBCOMP_PRP
  31. * 0 9 0 SET_SUBCOMP_PRP
  32. * 0 10 0 SET_SUBCOMP_PRP
  33. * 0 11 0 SET_SUBCOMP_PRP
  34. * 0 12 0 SET_SUBCOMP_PRP
  35. * 0 13 0 SET_SUBCOMP_PRP
  36. * 0 14 0 SET_SUBCOMP_PRP
  37. * 0.0 ==>_*r1Volt
  38. * 0.0 ==>_*r1Cur
  39. * ;
  40. *
  41. * :OUT_DATA
  42. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  43. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  44. * v_level *r1Volt f.<= if
  45. * 0 5 0 SET_SUBCOMP_PRP
  46. * 1 7 0 SET_SUBCOMP_PRP
  47. * 1 8 0 SET_SUBCOMP_PRP
  48. * 1 9 0 SET_SUBCOMP_PRP
  49. * 1 10 0 SET_SUBCOMP_PRP
  50. * 1 11 0 SET_SUBCOMP_PRP
  51. * 1 12 0 SET_SUBCOMP_PRP
  52. * 1 13 0 SET_SUBCOMP_PRP
  53. * 1 14 0 SET_SUBCOMP_PRP
  54. * else
  55. * 1 5 0 SET_SUBCOMP_PRP
  56. * 0 7 0 SET_SUBCOMP_PRP
  57. * 0 8 0 SET_SUBCOMP_PRP
  58. * 0 9 0 SET_SUBCOMP_PRP
  59. * 0 10 0 SET_SUBCOMP_PRP
  60. * 0 11 0 SET_SUBCOMP_PRP
  61. * 0 12 0 SET_SUBCOMP_PRP
  62. * 0 13 0 SET_SUBCOMP_PRP
  63. * 0 14 0 SET_SUBCOMP_PRP
  64. * endif
  65. * ;
  66. *
  67. * :BEGIN_PLOT
  68. * UPDATE_SETTINGS
  69. * ;
  70. * !!!END-INTERACT
  71. xX7 4 ProbeX7
  72. .subckt ProbeX7 1
  73. R1 1 0 1e12
  74. .ends
  75.  
  76. *## Multisim Component X3 ##*
  77. * !!!BEGIN-INTERACT
  78. * : v_level ++++f2 ;
  79. * 0.0 VARIABLE r1Volt
  80. * 0.0 VARIABLE r1Cur
  81. *
  82. * :UPDATE_SETTINGS
  83. * 1 5 0 SET_SUBCOMP_PRP
  84. * 0 7 0 SET_SUBCOMP_PRP
  85. * 0 8 0 SET_SUBCOMP_PRP
  86. * 0 9 0 SET_SUBCOMP_PRP
  87. * 0 10 0 SET_SUBCOMP_PRP
  88. * 0 11 0 SET_SUBCOMP_PRP
  89. * 0 12 0 SET_SUBCOMP_PRP
  90. * 0 13 0 SET_SUBCOMP_PRP
  91. * 0 14 0 SET_SUBCOMP_PRP
  92. * 0.0 ==>_*r1Volt
  93. * 0.0 ==>_*r1Cur
  94. * ;
  95. *
  96. * :OUT_DATA
  97. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  98. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  99. * v_level *r1Volt f.<= if
  100. * 0 5 0 SET_SUBCOMP_PRP
  101. * 1 7 0 SET_SUBCOMP_PRP
  102. * 1 8 0 SET_SUBCOMP_PRP
  103. * 1 9 0 SET_SUBCOMP_PRP
  104. * 1 10 0 SET_SUBCOMP_PRP
  105. * 1 11 0 SET_SUBCOMP_PRP
  106. * 1 12 0 SET_SUBCOMP_PRP
  107. * 1 13 0 SET_SUBCOMP_PRP
  108. * 1 14 0 SET_SUBCOMP_PRP
  109. * else
  110. * 1 5 0 SET_SUBCOMP_PRP
  111. * 0 7 0 SET_SUBCOMP_PRP
  112. * 0 8 0 SET_SUBCOMP_PRP
  113. * 0 9 0 SET_SUBCOMP_PRP
  114. * 0 10 0 SET_SUBCOMP_PRP
  115. * 0 11 0 SET_SUBCOMP_PRP
  116. * 0 12 0 SET_SUBCOMP_PRP
  117. * 0 13 0 SET_SUBCOMP_PRP
  118. * 0 14 0 SET_SUBCOMP_PRP
  119. * endif
  120. * ;
  121. *
  122. * :BEGIN_PLOT
  123. * UPDATE_SETTINGS
  124. * ;
  125. * !!!END-INTERACT
  126. xX3 3 ProbeX3
  127. .subckt ProbeX3 1
  128. R1 1 0 1e12
  129. .ends
  130.  
  131. *## Multisim Component U2 ##*
  132. xU2 5 DIGITAL_CLOCK__DIGITAL_SOURCES__1 PARAMS: Frequency=20 Duty=50 Delay=0
  133.  
  134.  
  135. *## Multisim Component U4 ##*
  136. aU4 6 d_constsource_U4
  137. .model d_constsource_U4 d_constsource(state=1)
  138.  
  139.  
  140. *## Multisim Component X2 ##*
  141. * !!!BEGIN-INTERACT
  142. * : v_level ++++f2 ;
  143. * 0.0 VARIABLE r1Volt
  144. * 0.0 VARIABLE r1Cur
  145. *
  146. * :UPDATE_SETTINGS
  147. * 1 5 0 SET_SUBCOMP_PRP
  148. * 0 7 0 SET_SUBCOMP_PRP
  149. * 0 8 0 SET_SUBCOMP_PRP
  150. * 0 9 0 SET_SUBCOMP_PRP
  151. * 0 10 0 SET_SUBCOMP_PRP
  152. * 0 11 0 SET_SUBCOMP_PRP
  153. * 0 12 0 SET_SUBCOMP_PRP
  154. * 0 13 0 SET_SUBCOMP_PRP
  155. * 0 14 0 SET_SUBCOMP_PRP
  156. * 0.0 ==>_*r1Volt
  157. * 0.0 ==>_*r1Cur
  158. * ;
  159. *
  160. * :OUT_DATA
  161. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  162. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  163. * v_level *r1Volt f.<= if
  164. * 0 5 0 SET_SUBCOMP_PRP
  165. * 1 7 0 SET_SUBCOMP_PRP
  166. * 1 8 0 SET_SUBCOMP_PRP
  167. * 1 9 0 SET_SUBCOMP_PRP
  168. * 1 10 0 SET_SUBCOMP_PRP
  169. * 1 11 0 SET_SUBCOMP_PRP
  170. * 1 12 0 SET_SUBCOMP_PRP
  171. * 1 13 0 SET_SUBCOMP_PRP
  172. * 1 14 0 SET_SUBCOMP_PRP
  173. * else
  174. * 1 5 0 SET_SUBCOMP_PRP
  175. * 0 7 0 SET_SUBCOMP_PRP
  176. * 0 8 0 SET_SUBCOMP_PRP
  177. * 0 9 0 SET_SUBCOMP_PRP
  178. * 0 10 0 SET_SUBCOMP_PRP
  179. * 0 11 0 SET_SUBCOMP_PRP
  180. * 0 12 0 SET_SUBCOMP_PRP
  181. * 0 13 0 SET_SUBCOMP_PRP
  182. * 0 14 0 SET_SUBCOMP_PRP
  183. * endif
  184. * ;
  185. *
  186. * :BEGIN_PLOT
  187. * UPDATE_SETTINGS
  188. * ;
  189. * !!!END-INTERACT
  190. xX2 2 ProbeX2
  191. .subckt ProbeX2 1
  192. R1 1 0 1e12
  193. .ends
  194.  
  195. *## Multisim Component X1 ##*
  196. * !!!BEGIN-INTERACT
  197. * : v_level ++++f2 ;
  198. * 0.0 VARIABLE r1Volt
  199. * 0.0 VARIABLE r1Cur
  200. *
  201. * :UPDATE_SETTINGS
  202. * 1 5 0 SET_SUBCOMP_PRP
  203. * 0 7 0 SET_SUBCOMP_PRP
  204. * 0 8 0 SET_SUBCOMP_PRP
  205. * 0 9 0 SET_SUBCOMP_PRP
  206. * 0 10 0 SET_SUBCOMP_PRP
  207. * 0 11 0 SET_SUBCOMP_PRP
  208. * 0 12 0 SET_SUBCOMP_PRP
  209. * 0 13 0 SET_SUBCOMP_PRP
  210. * 0 14 0 SET_SUBCOMP_PRP
  211. * 0.0 ==>_*r1Volt
  212. * 0.0 ==>_*r1Cur
  213. * ;
  214. *
  215. * :OUT_DATA
  216. * GET_INSTANCE Resistor ::R r1 i ==>_*r1Cur
  217. * 1.0e12 *r1Cur f.* ==>_*r1Volt
  218. * v_level *r1Volt f.<= if
  219. * 0 5 0 SET_SUBCOMP_PRP
  220. * 1 7 0 SET_SUBCOMP_PRP
  221. * 1 8 0 SET_SUBCOMP_PRP
  222. * 1 9 0 SET_SUBCOMP_PRP
  223. * 1 10 0 SET_SUBCOMP_PRP
  224. * 1 11 0 SET_SUBCOMP_PRP
  225. * 1 12 0 SET_SUBCOMP_PRP
  226. * 1 13 0 SET_SUBCOMP_PRP
  227. * 1 14 0 SET_SUBCOMP_PRP
  228. * else
  229. * 1 5 0 SET_SUBCOMP_PRP
  230. * 0 7 0 SET_SUBCOMP_PRP
  231. * 0 8 0 SET_SUBCOMP_PRP
  232. * 0 9 0 SET_SUBCOMP_PRP
  233. * 0 10 0 SET_SUBCOMP_PRP
  234. * 0 11 0 SET_SUBCOMP_PRP
  235. * 0 12 0 SET_SUBCOMP_PRP
  236. * 0 13 0 SET_SUBCOMP_PRP
  237. * 0 14 0 SET_SUBCOMP_PRP
  238. * endif
  239. * ;
  240. *
  241. * :BEGIN_PLOT
  242. * UPDATE_SETTINGS
  243. * ;
  244. * !!!END-INTERACT
  245. xX1 1 ProbeX1
  246. .subckt ProbeX1 1
  247. R1 1 0 1e12
  248. .ends
  249.  
  250. *## Multisim Component U1 ##*
  251. aU1 [5
  252. + 6
  253. + 6
  254. + 6
  255. + dU1.notLOAD
  256. + 6
  257. + 6
  258. + U1_OPEN_C
  259. + U1_OPEN_D]
  260. + [dU1.QA
  261. + dU1.QB
  262. + dU1.QC
  263. + U1_OPEN_QD
  264. + U1_OPEN_RCO] 74160__74STD__1
  265.  
  266. xU1.QA dU1.QA 1 VCC GND TTL_DRV__NON__1
  267.  
  268.  
  269. xU1.QB dU1.QB 2 VCC GND TTL_DRV__NON__1
  270.  
  271.  
  272. xU1.QC dU1.QC 3 VCC GND TTL_DRV__NON__1
  273.  
  274.  
  275.  
  276.  
  277.  
  278.  
  279.  
  280.  
  281.  
  282.  
  283. xU1.notLOAD 4 dU1.notLOAD VCC GND TTL_RCV__NON__1
  284.  
  285.  
  286.  
  287.  
  288.  
  289. .SUBCKT TTL_DRV__NON__1 1 2 3 4
  290. * TTL Driver Model 1 = D/A input, 2 = out 3= VCC 4 = VSS(GND)
  291. *#L1
  292. aDAC1in [1] [2] aDAC1
  293. .MODEL aDAC1 dac_bridge (out_low= 0 out_high = 5 out_undef = 2.5)
  294. *#L1
  295.  
  296. .ENDS
  297.  
  298. .SUBCKT TTL_RCV__NON__1 1 2 3 4
  299. * Receiver 1 = input, 2 = A/D out 3 = VCC 4 = VSS(GND)
  300. *#L1
  301. aADC1in [1] [2] ADC1
  302. .MODEL ADC1 adc_bridge (in_low= 2.5 in_high = 2.5)
  303. *#L1
  304.  
  305. .ENDS
  306.  
  307. .model 74LS386__74STD__1 d_chip ( behaviour= "
  308. +; 74LS386 QUAD 2-INPUT XOR
  309. +/inputs A B
  310. +/outputs Y
  311. +/table 4
  312. +; A B Y
  313. + L L L
  314. + L H H
  315. + H L H
  316. + H H L
  317. +/Conditional_Delay 8
  318. +;event to condition output min/max time
  319. + LH A (B=L) Y max 23n
  320. + HL A (B=L) Y max 17n
  321. + LH A (B=H) Y max 30n
  322. + HL A (B=H) Y max 22n
  323. + LH B (A=L) Y max 23n
  324. + HL B (A=L) Y max 17n
  325. + LH B (A=H) Y max 30n
  326. + HL B (A=H) Y max 22n
  327. +")
  328.  
  329. .subckt DIGITAL_CLOCK__DIGITAL_SOURCES__1 out PARAMS: Frequency=1k Duty=50 Delay=0
  330. A1 out DigClock
  331. .model DigClock d_clock (frequency={Frequency} duty={Duty/100} delay={Delay})
  332. .ends
  333.  
  334. .MODEL 74160__74STD__1 d_chip ( behaviour= "
  335. +; 74160 SYNCHRONOUS 4-BIT COUNTER BCD - ASYNC CLEAR
  336. +/inputs CLK ~CLR ENT ENP ~LOAD A B C D
  337. +/outputs QA QB QC QD RCO
  338. +/wires WQA WQB WQC WQD
  339. +/module CNTR_CORE
  340. +/inputs CLK ~CLR ENT ENP ~LOAD A B C D
  341. +/outputs QA QB QC QD
  342. +/clock CLK - 4 10 2
  343. +;SYNC
  344. +; CLK ~CLR ENT ENP ~LOAD ABCD FFFF NF NF NF NF
  345. + X H X X L XXXX XXXX A B C D
  346. + X H H H H XXXX HHHH L L L L
  347. + X H H H H XXXX LHHH L L L L
  348. + X H H H H XXXX HLHH L L L L
  349. + X H H H H XXXX LLHH L L L L
  350. + X H H H H XXXX HHLH L L L L
  351. + X H H H H XXXX LHLH L L L L
  352. + X H H H H XXXX HLLH L L L L
  353. + X H H H H XXXX XXXX F+0 F+1 F+2 F+3
  354. + X X X X X XXXX XXXX F0 F1 F2 F3
  355. +;ASYNC
  356. +; CLK ~CLR ENT ENP ~LOAD DCBA FFFF NF NF NF NF
  357. + X L X X X XXXX XXXX L L L L
  358. + X X X X X XXXX XXXX F0 F1 F2 F3
  359. +/TABLE 1
  360. +; CLK ~CLR ENT ENP ~LOAD DCBA FFFF QA QB QC QD
  361. + X X X X X XXXX XXXX F0 F1 F2 F3
  362. +/delay 4
  363. +;input output Rise time Fall time
  364. + ~CLR QA X 38n
  365. + ~CLR QB X 38n
  366. + ~CLR QC X 38n
  367. + ~CLR QD X 38n
  368. +/conditional_delay 16
  369. +;event to condition output min/max time
  370. + LH CLK (~LOAD=L) QA MAX 20n
  371. + LH CLK (~LOAD=L) QB MAX 20n
  372. + LH CLK (~LOAD=L) QC MAX 20n
  373. + LH CLK (~LOAD=L) QD MAX 20n
  374. + HL CLK (~LOAD=L) QA MAX 23n
  375. + HL CLK (~LOAD=L) QB MAX 23n
  376. + HL CLK (~LOAD=L) QC MAX 23n
  377. + HL CLK (~LOAD=L) QD MAX 23n
  378. + LH CLK (~LOAD=H) QA MAX 25n
  379. + LH CLK (~LOAD=H) QB MAX 25n
  380. + LH CLK (~LOAD=H) QC MAX 25n
  381. + LH CLK (~LOAD=H) QD MAX 25n
  382. + HL CLK (~LOAD=H) QA MAX 29n
  383. + HL CLK (~LOAD=H) QB MAX 29n
  384. + HL CLK (~LOAD=H) QC MAX 29n
  385. + HL CLK (~LOAD=H) QD MAX 29n
  386. +/constraint 24
  387. +; Name Event From Event To Min/Max Time
  388. + 'PULSE WIDTH' HL CLK LH CLK MIN 25n
  389. + 'PULSE WIDTH' HL ~CLR LH ~CLR MIN 20n
  390. + 'SETUP' LH A LH CLK MIN 20n
  391. + 'SETUP' LH B LH CLK MIN 20n
  392. + 'SETUP' LH C LH CLK MIN 20n
  393. + 'SETUP' LH D LH CLK MIN 20n
  394. + 'SETUP' HL A LH CLK MIN 20n
  395. + 'SETUP' HL B LH CLK MIN 20n
  396. + 'SETUP' HL C LH CLK MIN 20n
  397. + 'SETUP' HL D LH CLK MIN 20n
  398. + 'SETUP' LH ENT LH CLK MIN 20n
  399. + 'SETUP' LH ENP LH CLK MIN 20n
  400. + 'SETUP' HL ~LOAD LH CLK MIN 25n
  401. + 'SETUP' HL ~CLR LH CLK MIN 20n
  402. + 'HOLD' LH CLK HL A MIN 0n
  403. + 'HOLD' LH CLK HL B MIN 0n
  404. + 'HOLD' LH CLK HL C MIN 0n
  405. + 'HOLD' LH CLK HL D MIN 0n
  406. + 'HOLD' LH CLK LH A MIN 0n
  407. + 'HOLD' LH CLK LH B MIN 0n
  408. + 'HOLD' LH CLK LH C MIN 0n
  409. + 'HOLD' LH CLK LH D MIN 0n
  410. + 'HOLD' LH CLK LH ~LOAD MIN 0n
  411. + 'HOLD' LH CLK LH ~CLR MIN 0n
  412. +/endmodule
  413. +/module RCO_OUT
  414. +/inputs ENT ENP ~LOAD A B C D
  415. +/outputs RCO
  416. +/table 2
  417. +; ENT ENP ~LOAD ABCD RCO
  418. + H H H HLLH H
  419. + X X X XXXX L
  420. +/delay 1
  421. + ENT RCO 16n 16n
  422. +/endmodule
  423. +/module BUFF_OUT
  424. +/inputs A
  425. +/outputs Y
  426. +/table 2
  427. +; A Y
  428. + L L
  429. + H H
  430. +/endmodule
  431. +/instance CNTR_CORE CLK ~CLR ENT ENP ~LOAD A B C D WQA WQB WQC WQD
  432. +/instance RCO_OUT ENT ENP ~LOAD WQA WQB WQC WQD RCO
  433. +/instance BUFF_OUT WQA QA
  434. +/instance BUFF_OUT WQB QB
  435. +/instance BUFF_OUT WQC QC
  436. +/instance BUFF_OUT WQD QD
  437. +")
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