module main_0002_mmul_fsm (
    input wire bus2ip_clk_i,
    input wire bus2ip_reset_i,
    output reg [17:0] ip2fsm_dma_addr_o,
    output reg [71:0] ip2fsm_data_o,
    output reg [1:0] ip2fsm_write_req_o,
    input wire fsm2ip_dma_wr_ack_i,
    input wire [71:0] fsm2ip_data_i,
    output reg [1:0] ip2fsm_read_req_o,
    input wire fsm2ip_dma_rd_ack_i,
    input wire start_i,
    output reg ready_o,
    output reg running_o,
    input wire [17:0] m1_13_i,
    input wire [17:0] m2_18_i,
    input wire [17:0] res_26_i,
    output reg signed [17:0] exit_bb_idx_o
);

localparam [17:0] BITS_PER_WORD = 18;


/* begin parameter */
parameter [4:0] IDLE = 0;
parameter [4:0] ST_1 = 1;
parameter [4:0] ST_2 = 2;
parameter [4:0] ST_3 = 3;
parameter [4:0] ST_4 = 4;
parameter [4:0] ST_5 = 5;
parameter [4:0] ST_6 = 6;
parameter [4:0] ST_7 = 7;
parameter [4:0] ST_8 = 8;
parameter [4:0] ST_9 = 9;
parameter [4:0] ST_10 = 10;
parameter [4:0] ST_11 = 11;
parameter [4:0] ST_12 = 12;
parameter [4:0] ST_13 = 13;
parameter [4:0] ST_14 = 14;
parameter [4:0] ST_15 = 15;
parameter [4:0] ST_16 = 16;
parameter [4:0] ST_17 = 17;
parameter [4:0] ST_18 = 18;
parameter [4:0] ST_19 = 19;
parameter [4:0] ST_20 = 20;
parameter [4:0] ST_21 = 21;
parameter [4:0] ST_22 = 22;
parameter [4:0] ST_23 = 23;
/* end parameter */

/* begin registers */
reg  [4:0] current_state;
reg  [4:0] next_state;
reg   next_running;
reg start_ff1;
reg start_rising_edge;
reg  [17:0] next_exit_bb_idx_o;
reg  [17:0] next_ip2fsm_dma_addr;
reg  [17:0] global_reg_1;
reg  [17:0] next_global_reg_1;
reg  [17:0] global_reg_2;
reg  [17:0] next_global_reg_2;
reg  [17:0] global_reg_3;
reg  [17:0] next_global_reg_3;
reg  [17:0] global_reg_4;
reg  [17:0] next_global_reg_4;
reg  [17:0] global_reg_5;
reg  [17:0] next_global_reg_5;
reg  [17:0] global_reg_6;
reg  [17:0] next_global_reg_6;
reg signed [17:0] global_reg_7;
reg signed [17:0] next_global_reg_7;
reg  [17:0] global_reg_8;
reg  [17:0] next_global_reg_8;
reg  [17:0] global_reg_9;
reg  [17:0] next_global_reg_9;
reg  [17:0] global_reg_10;
reg  [17:0] next_global_reg_10;
reg  [17:0] global_reg_11;
reg  [17:0] next_global_reg_11;
reg signed [17:0] global_reg_12;
reg signed [17:0] next_global_reg_12;
reg signed [17:0] global_reg_13;
reg signed [17:0] next_global_reg_13;
reg  [17:0] global_reg_14;
reg  [17:0] next_global_reg_14;
reg  [17:0] global_reg_15;
reg  [17:0] next_global_reg_15;
reg  [17:0] global_reg_16;
reg  [17:0] next_global_reg_16;
reg  [17:0] global_reg_17;
reg  [17:0] next_global_reg_17;
reg  [17:0] global_reg_18;
reg  [17:0] next_global_reg_18;
reg signed [17:0] global_reg_19;
reg signed [17:0] next_global_reg_19;
reg signed [17:0] global_reg_20;
reg signed [17:0] next_global_reg_20;
reg signed [17:0] global_reg_21;
reg signed [17:0] next_global_reg_21;
reg  [17:0] global_reg_22;
reg  [17:0] next_global_reg_22;
reg  [17:0] global_reg_23;
reg  [17:0] next_global_reg_23;
reg  [17:0] global_reg_24;
reg  [17:0] next_global_reg_24;
reg  [17:0] global_reg_25;
reg  [17:0] next_global_reg_25;
reg  [17:0] global_reg_26;
reg  [17:0] next_global_reg_26;
reg  [17:0] global_reg_27;
reg  [17:0] next_global_reg_27;
reg  [17:0] global_reg_28;
reg  [17:0] next_global_reg_28;
reg  [17:0] global_reg_29;
reg  [17:0] next_global_reg_29;
reg  [17:0] global_reg_30;
reg  [17:0] next_global_reg_30;
reg  [17:0] global_reg_31;
reg  [17:0] next_global_reg_31;
/* end registers */

/* begin submodule registers */
/* end submodule registers */

/* begin submodules */
/* end submodules */

/* begin FSM control logic */
always @(posedge bus2ip_clk_i or posedge bus2ip_reset_i)
begin:FSM_CTRL
    if(bus2ip_reset_i)
        begin
            current_state <= IDLE;
            start_ff1 <= 0;
            start_rising_edge <= 0;
            exit_bb_idx_o <= 0;
            running_o <= 0;
        end
    else
        begin
            current_state <= next_state;
            running_o <= next_running;
            start_ff1 <= start_i;
            start_rising_edge <= start_i & ~start_ff1;
            global_reg_1 <= next_global_reg_1;
            global_reg_2 <= next_global_reg_2;
            global_reg_3 <= next_global_reg_3;
            global_reg_4 <= next_global_reg_4;
            global_reg_5 <= next_global_reg_5;
            global_reg_6 <= next_global_reg_6;
            global_reg_7 <= next_global_reg_7;
            global_reg_8 <= next_global_reg_8;
            global_reg_9 <= next_global_reg_9;
            global_reg_10 <= next_global_reg_10;
            global_reg_11 <= next_global_reg_11;
            global_reg_12 <= next_global_reg_12;
            global_reg_13 <= next_global_reg_13;
            global_reg_14 <= next_global_reg_14;
            global_reg_15 <= next_global_reg_15;
            global_reg_16 <= next_global_reg_16;
            global_reg_17 <= next_global_reg_17;
            global_reg_18 <= next_global_reg_18;
            global_reg_19 <= next_global_reg_19;
            global_reg_20 <= next_global_reg_20;
            global_reg_21 <= next_global_reg_21;
            global_reg_22 <= next_global_reg_22;
            global_reg_23 <= next_global_reg_23;
            global_reg_24 <= next_global_reg_24;
            global_reg_25 <= next_global_reg_25;
            global_reg_26 <= next_global_reg_26;
            global_reg_27 <= next_global_reg_27;
            global_reg_28 <= next_global_reg_28;
            global_reg_29 <= next_global_reg_29;
            global_reg_30 <= next_global_reg_30;
            global_reg_31 <= next_global_reg_31;
            next_ip2fsm_dma_addr <= ip2fsm_dma_addr_o;
            exit_bb_idx_o <= next_exit_bb_idx_o;

        end
end
/* end FSM control logic */

/* begin FSM out logic */
always@(*)

begin:OUT_LOGIC
    ip2fsm_data_o <= 0;
    ip2fsm_write_req_o <= 0;
    ip2fsm_read_req_o <= 0;
    next_state <= current_state;
    next_running <= running_o;
    ready_o <= 0;
    next_global_reg_1 <= global_reg_1;
    next_global_reg_2 <= global_reg_2;
    next_global_reg_3 <= global_reg_3;
    next_global_reg_4 <= global_reg_4;
    next_global_reg_5 <= global_reg_5;
    next_global_reg_6 <= global_reg_6;
    next_global_reg_7 <= global_reg_7;
    next_global_reg_8 <= global_reg_8;
    next_global_reg_9 <= global_reg_9;
    next_global_reg_10 <= global_reg_10;
    next_global_reg_11 <= global_reg_11;
    next_global_reg_12 <= global_reg_12;
    next_global_reg_13 <= global_reg_13;
    next_global_reg_14 <= global_reg_14;
    next_global_reg_15 <= global_reg_15;
    next_global_reg_16 <= global_reg_16;
    next_global_reg_17 <= global_reg_17;
    next_global_reg_18 <= global_reg_18;
    next_global_reg_19 <= global_reg_19;
    next_global_reg_20 <= global_reg_20;
    next_global_reg_21 <= global_reg_21;
    next_global_reg_22 <= global_reg_22;
    next_global_reg_23 <= global_reg_23;
    next_global_reg_24 <= global_reg_24;
    next_global_reg_25 <= global_reg_25;
    next_global_reg_26 <= global_reg_26;
    next_global_reg_27 <= global_reg_27;
    next_global_reg_28 <= global_reg_28;
    next_global_reg_29 <= global_reg_29;
    next_global_reg_30 <= global_reg_30;
    next_global_reg_31 <= global_reg_31;
    ip2fsm_dma_addr_o <= next_ip2fsm_dma_addr;
    next_exit_bb_idx_o <= exit_bb_idx_o;
    case(current_state)
        IDLE:begin
            ready_o <= 1;
             next_running <= 0;
            ip2fsm_dma_addr_o <= 0;
            if(start_rising_edge)
            begin
                ready_o <= 0;
                next_running <= 1;
                next_state <= ST_1;
                next_global_reg_2 <= m2_18_i;
                next_global_reg_3 <= res_26_i;
                next_global_reg_16 <= 18'd0;
                next_global_reg_1 <= m1_13_i;
            end
            end
        ST_1:begin //(null)
            next_global_reg_27 <= global_reg_1;
            next_global_reg_26 <= global_reg_3;
            next_global_reg_4 <= 18'd0;
            next_state <= ST_2;
            end
        ST_2:begin //(null)
            next_global_reg_29 <= global_reg_27 + global_reg_16;
            next_global_reg_28 <= global_reg_16 + global_reg_26;
            next_state <= ST_3;
            end
        ST_3:begin //(null)
            next_global_reg_31 <= global_reg_29;
            next_global_reg_30 <= global_reg_28;
            next_state <= ST_4;
            end
        ST_4:begin //(null)
            next_global_reg_5 <= global_reg_31;
            next_global_reg_6 <= global_reg_30;
            next_state <= ST_5;
            next_state <= ST_5;
            end
        ST_5:begin //(null)
            next_global_reg_23 <= global_reg_2;
            next_global_reg_7 <= 18'd0;
            next_global_reg_8 <= 18'd0;
            next_state <= ST_6;
            end
        ST_6:begin //(null)
            next_global_reg_24 <= global_reg_23 + global_reg_4;
            next_state <= ST_7;
            end
        ST_7:begin //(null)
            next_global_reg_25 <= global_reg_24;
            next_state <= ST_8;
            end
        ST_8:begin //(null)
            next_global_reg_9 <= global_reg_25;
            next_state <= ST_9;
            next_state <= ST_9;
            end
        ST_9:begin //(null)
            next_global_reg_17 <= global_reg_5 + global_reg_8;
            next_global_reg_18 <= global_reg_9;
            next_global_reg_11 <= global_reg_8 + 18'd2;
            next_global_reg_10 <= global_reg_9 + 18'd16;
            next_state <= ST_10;
            end
        ST_10:begin //(null)
            ip2fsm_dma_addr_o <= (global_reg_17 );
            next_state <= ST_11;
            end
        ST_11:begin //(null)
            ip2fsm_read_req_o <= 5'd2;
            next_global_reg_19 <= fsm2ip_data_i;
            ip2fsm_dma_addr_o <= (global_reg_18 );
            if (!fsm2ip_dma_rd_ack_i)
            begin
                ip2fsm_dma_addr_o <= (global_reg_17 );
                next_state <= ST_11;
            end
            else
            begin
                next_state <= ST_12;
            end
            end
        ST_12:begin //(null)
            ip2fsm_read_req_o <= 5'd2;
            next_global_reg_20 <= fsm2ip_data_i;
            if (!fsm2ip_dma_rd_ack_i)
            begin
                ip2fsm_dma_addr_o <= (global_reg_18 );
                next_state <= ST_12;
            end
            else
            begin
                next_state <= ST_13;
            end
            end
        ST_13:begin //(null)
            next_global_reg_21 <= global_reg_19 * global_reg_20;
            next_state <= ST_14;
            end
        ST_14:begin //(null)
            next_global_reg_12 <= global_reg_21 + global_reg_7;
            next_state <= ST_15;
            end
        ST_15:begin //(null)
            next_global_reg_13 <= global_reg_12;
            if (global_reg_11 != 16)
            begin
                next_state <= ST_16;
            end
            else if (global_reg_11 == 16)
            begin
                next_state <= ST_17;
            end
            end
        ST_16:begin //(null)
            next_global_reg_7 <= global_reg_12;
            next_global_reg_8 <= global_reg_11;
            next_global_reg_9 <= global_reg_10;
            next_state <= ST_9;
            end
        ST_17:begin //(null)
            next_global_reg_22 <= global_reg_6 + global_reg_4;
            next_global_reg_14 <= global_reg_4 + 18'd2;
            next_state <= ST_18;
            end
        ST_18:begin //(null)
            ip2fsm_dma_addr_o <= (global_reg_22 );
            ip2fsm_write_req_o <= 5'd2;
            ip2fsm_data_o <= global_reg_13;
            if (fsm2ip_dma_wr_ack_i == 1'b0)
            begin
                next_state <= ST_18;
            end
            else if (global_reg_14 != 16)
            begin
                next_state <= ST_19;
            end
            else if (global_reg_14 == 16)
            begin
                next_state <= ST_20;
            end
            end
        ST_19:begin //(null)
            next_global_reg_4 <= global_reg_14;
            next_state <= ST_5;
            end
        ST_20:begin //(null)
            next_global_reg_15 <= global_reg_16 + 18'd16;
            next_state <= ST_21;
            end
        ST_21:begin //(null)
            if (global_reg_15 != 128)
            begin
                next_state <= ST_23;
            end
            else if (global_reg_15 == 128)
            begin
                next_state <= ST_22;
            end
            end
        ST_22:begin //(null)
            next_state <= IDLE;
            next_exit_bb_idx_o <= 8;
            end
        ST_23:begin //(null)
            next_global_reg_16 <= global_reg_15;
            next_state <= ST_1;
            end

    endcase
end
/* end FSM out logic */

endmodule