library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity pwm is

port( writedata: in std_logic_vector(31 downto 0);
      clk_clk, reset_reset_n:   in std_logic;
      wr, cs : in std_logic;
      pwm_out: out std_logic;
		hex : out std_logic_vector(6 downto 0));
end pwm;



architecture rtl of pwm is
signal reg: std_logic_vector(3 downto 0);
signal licznik: std_logic_vector(25 downto 0);
	begin
	process(clk_clk)
	begin

		if (clk_clk'event and clk_clk='1') then
			if(wr='1' and cs='1') then
			  reg <=writedata(3 downto 0);
			  end if;

		 end if;

	end process;



process(clk_clk)
begin
   if (clk_clk'event and clk_clk='1') then

		if(reg="0001") then
			pwm_out <= '1';
			hex <= "1111001";
		else
			pwm_out <= '0';
			hex <= "1111111";
		end if;

    end if;
end process;

end rtl;