module div (
    input signed [31:0] A,
    input signed [31:0] B,
    input clk,
    input reset,
    input DivCon,
    output reg signed [31:0] hi,
    output reg signed [31:0] lo,
    output exc

);

reg signed [63:0] Div;
reg signed [63:0] Divs;
reg signed [31:0] quo;
reg signed [63:0] aux;
integer i;
initial begin
    i = 34;
end
always @ (posedge clk) begin
    if (reset == 1) begin
        Div = 64'b0;
        Divs = 64'b0;
        quo = 32'b0;
        aux = 64'b0;
    end
    if (DivCon == 1) begin
        if (i > 31) begin
            Div = {32'b0, A};
            Divs = {B, 32'b0};
            quo = 32'b0;
            i = 0;
        end
    end
    if (i < 32) begin
        aux = ~Divs + 1;
        aux = Div + aux;

        case (aux[63])
            1'b1: begin
                quo = quo <<< 1;
                Divs = Divs >>> 1;
            end
            1'b0: begin
                quo = quo <<< 1;
                Divs = Divs >>> 1;
                quo = {quo[31:1], 1'b1};
            end
        endcase
        i = i + 1;
        hi = i;
        if (i == 32) begin
            hi = quo;
            lo = aux[31:0];
        end
    end
end

endmodule //