`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   17:27:23 02/21/2018
// Design Name:   edgedetector_bh
// Module Name:   C:/Users/ulyana/Desktop/CS120A_Files/Lab 4/RisingEdgeDetect/edgeDetector.v
// Project Name:  RisingEdgeDetect
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: edgedetector_bh
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module edgeDetector;

	// Inputs
	reg clk;
	reg reset;
	reg signal;

	// Outputs
	wire outedge;

	// Instantiate the Unit Under Test (UUT)
	edgedetector_bh uut (
		.clk(clk),
		.reset(reset),
		.signal(signal),
		.outedge(outedge)
	);

	always begin
		clk = !clk;
		#1;
	end

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		signal = 0;

		// Wait 100 ns for global reset to finish
		#100;

		// Initialize Inputs
		reset = 0;
		signal = 1;

		// Wait 100 ns for global reset to finish
		#100;

		// Initialize Inputs
		reset = 0;
		signal = 1;

		// Wait 100 ns for global reset to finish
		#100;

		// Initialize Inputs
		reset = 1;
		signal = 1;

		// Wait 100 ns for global reset to finish
		#100;

		// Initialize Inputs
		reset = 1;
		signal = 0;

		// Wait 100 ns for global reset to finish
		#100;

		// Initialize Inputs
		reset = 0;
		signal = 1;

		// Wait 100 ns for global reset to finish
		#100;

	end

endmodule