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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 15:58:40 04/16/2009
  6. -- Design Name:
  7. -- Module Name: sistem - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_ARITH.ALL;
  23. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  24.  
  25. ---- Uncomment the following library declaration if instantiating
  26. ---- any Xilinx primitives in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29.  
  30. entity sistem is
  31. Port ( iCLK : in STD_LOGIC;
  32. inRST : in STD_LOGIC;
  33. iDATA : in STD_LOGIC;
  34. oA_GT_B : out STD_LOGIC;
  35. oA_EQ_B : out STD_LOGIC;
  36. oA_LT_B : out STD_LOGIC;
  37. oOUT_EN : out STD_LOGIC);
  38. end sistem;
  39.  
  40. architecture Behavioral of sistem is
  41. --BROJACKI SIGNALI
  42. SIGNAL sCNT : INTEGER RANGE 0 TO 7 := 0;
  43. CONSTANT cHIGH : INTEGER :=7;
  44. SIGNAL sTSE : STD_LOGIC;
  45.  
  46. --REGISTAR GENERATOR
  47. SIGNAL sREG_GEN : STD_LOGIC_VECTOR (7 DOWNTO 0);
  48. SIGNAL sOUT_EN : STD_LOGIC;
  49.  
  50. --SHIFT REGISTAR
  51. SIGNAL sREG : STD_LOGIC_VECTOR (7 DOWNTO 0);
  52.  
  53. begin
  54.  
  55. --BROJAC
  56. process (iCLK, inRST) begin
  57. if inRST='0' then
  58. sCNT<= 0;
  59. sTSE<='0';
  60. elsif iCLK='1' and iCLK'event then
  61. sCNT <= sCNT + 1;
  62. sTSE<='0';
  63. IF (sCNT=cHIGH) THEN
  64. sTSE<='1';
  65. sCNT<= 0;
  66. end if;
  67. end if;
  68. end process;
  69.  
  70. --GENERATOR
  71. process (iCLK, inRST) begin
  72. if iCLK='1' and iCLK'event then
  73. IF (inRST='0') THEN
  74. sREG_GEN<="00110100";
  75. sOUT_EN<='0';
  76. ELSIF (sTSE='1') THEN
  77. sREG_GEN<=sREG_GEN(6 DOWNTO 0) & (sREG(7) XOR sREG(6));
  78. sOUT_EN<='1';
  79. ELSE
  80. sOUT_EN<='0';
  81. sREG_GEN<=sREG_GEN;
  82. END IF;
  83. END IF;
  84. END PROCESS;
  85.  
  86. --GENERISANJE IZLAZA oOUT_EN
  87. oOUT_EN<=sOUT_EN;
  88.  
  89. --SHIFT REGISTER
  90. process (iCLK, inRST) begin
  91. if iCLK='1' and iCLK'event then
  92. IF (inRST='0') THEN
  93. sREG<="00000000";
  94. ELSE
  95. sREG<=iDATA & sREG(7 DOWNTO 1);
  96. END IF;
  97. END IF;
  98. END PROCESS;
  99.  
  100. --KOMPARATOR
  101. PROCESS (sREG, sREG_GEN, sOUT_EN) BEGIN
  102. IF sOUT_EN='1' THEN
  103. IF (sREG=sREG_GEN) THEN
  104. oA_EQ_B<='1';
  105. oA_LT_B<='0';
  106. oA_GT_B<='0';
  107. ELSIF (sREG<sREG_GEN) THEN
  108. oA_EQ_B<='0';
  109. oA_LT_B<='1';
  110. oA_GT_B<='0';
  111. ELSE
  112. oA_EQ_B<='0';
  113. oA_LT_B<='0';
  114. oA_GT_B<='1';
  115. END IF;
  116. END IF;
  117. END PROCESS;
  118.  
  119. end Behavioral;
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