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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 15:58:40 04/16/2009
- -- Design Name:
- -- Module Name: sistem - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- ---- Uncomment the following library declaration if instantiating
- ---- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity sistem is
- Port ( iCLK : in STD_LOGIC;
- inRST : in STD_LOGIC;
- iDATA : in STD_LOGIC;
- oA_GT_B : out STD_LOGIC;
- oA_EQ_B : out STD_LOGIC;
- oA_LT_B : out STD_LOGIC;
- oOUT_EN : out STD_LOGIC);
- end sistem;
- architecture Behavioral of sistem is
- --BROJACKI SIGNALI
- SIGNAL sCNT : INTEGER RANGE 0 TO 7 := 0;
- CONSTANT cHIGH : INTEGER :=7;
- SIGNAL sTSE : STD_LOGIC;
- --REGISTAR GENERATOR
- SIGNAL sREG_GEN : STD_LOGIC_VECTOR (7 DOWNTO 0);
- SIGNAL sOUT_EN : STD_LOGIC;
- --SHIFT REGISTAR
- SIGNAL sREG : STD_LOGIC_VECTOR (7 DOWNTO 0);
- begin
- --BROJAC
- process (iCLK, inRST) begin
- if inRST='0' then
- sCNT<= 0;
- sTSE<='0';
- elsif iCLK='1' and iCLK'event then
- sCNT <= sCNT + 1;
- sTSE<='0';
- IF (sCNT=cHIGH) THEN
- sTSE<='1';
- sCNT<= 0;
- end if;
- end if;
- end process;
- --GENERATOR
- process (iCLK, inRST) begin
- if iCLK='1' and iCLK'event then
- IF (inRST='0') THEN
- sREG_GEN<="00110100";
- sOUT_EN<='0';
- ELSIF (sTSE='1') THEN
- sREG_GEN<=sREG_GEN(6 DOWNTO 0) & (sREG(7) XOR sREG(6));
- sOUT_EN<='1';
- ELSE
- sOUT_EN<='0';
- sREG_GEN<=sREG_GEN;
- END IF;
- END IF;
- END PROCESS;
- --GENERISANJE IZLAZA oOUT_EN
- oOUT_EN<=sOUT_EN;
- --SHIFT REGISTER
- process (iCLK, inRST) begin
- if iCLK='1' and iCLK'event then
- IF (inRST='0') THEN
- sREG<="00000000";
- ELSE
- sREG<=iDATA & sREG(7 DOWNTO 1);
- END IF;
- END IF;
- END PROCESS;
- --KOMPARATOR
- PROCESS (sREG, sREG_GEN, sOUT_EN) BEGIN
- IF sOUT_EN='1' THEN
- IF (sREG=sREG_GEN) THEN
- oA_EQ_B<='1';
- oA_LT_B<='0';
- oA_GT_B<='0';
- ELSIF (sREG<sREG_GEN) THEN
- oA_EQ_B<='0';
- oA_LT_B<='1';
- oA_GT_B<='0';
- ELSE
- oA_EQ_B<='0';
- oA_LT_B<='0';
- oA_GT_B<='1';
- END IF;
- END IF;
- END PROCESS;
- end Behavioral;
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