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  1. module runner;
  2.     reg [3:0] a, b;
  3.     reg [3:0] func;
  4.     wire [7:0] alu_out;
  5.     wire [6:0] hex1_out, hex2_out;
  6.    
  7.     integer _a, _b;
  8.     ALU my_alu(a, b, 0, alu_out);
  9.     hex_display hex1(alu_out[3:0], hex1_out);
  10.     hex_display hex2(alu_out[7:4], hex2_out);
  11.     initial
  12.     begin
  13.         #1 $monitor("a=%b b=%b out=%b hex2=%b, hex1=%b", a, b, alu_out, hex2_out, hex1_out);
  14.         for (_a = 0; _a < 16; _a = _a + 1)
  15.         begin
  16.             for (_b = 0; _b < 16; _b = _b + 1)
  17.             begin
  18.                 a = _a; b = _b;
  19.                 #1;
  20.             end
  21.         end
  22.     end
  23. endmodule
  24.  
  25. module ALU(a, b, f, out);
  26.     input [3:0] a, b, f;
  27.     output [7:0] out;
  28.     reg out;
  29.    
  30.     wire [7:0] result0, result1, result2, result3, result4, result5;
  31.     reg [7:0] has_1, all_1;
  32.    
  33.     Adder5Bit my_adder(a, b, 1'b0, result0);
  34.     assign result1 = a + b;
  35.     assign result2 = {a | b,  a ^ b};
  36.     assign result3 = | {a, b};
  37.     assign result4 = & {a, b};
  38.     assign result5 = {a, b};
  39.    
  40.     always @ (*)
  41.     begin
  42.         case(f)
  43.             'd0: out = result0;
  44.             'd1: out = result1;
  45.             'd2: out = result2;
  46.             'd3: out = result3;
  47.             'd4: out = result4;
  48.             'd5: out = result5;
  49.             default: out = 'b0;
  50.         endcase
  51.     end
  52.    
  53. endmodule
  54.  
  55.  
  56. module Adder5Bit(a, b, cin, out);
  57.     input [3:0] a, b;
  58.     input cin;
  59.     output [4:0] out;
  60.     wire cout;
  61.    
  62.     wire _carry1, _carry2, _carry3, _carry4;
  63.    
  64.     FullAdder bit1(a[0], b[0], cin, out[0], _carry1);
  65.     FullAdder bit2(a[1], b[1], _carry1, out[1], _carry2);
  66.     FullAdder bit3(a[2], b[2], _carry2, out[2], _carry3);
  67.     FullAdder bit4(a[3], b[3], _carry3, out[3], _carry4);
  68.     FullAdder bit5('b0, 'b0, _carry4, out[4], cout);
  69. endmodule
  70.  
  71. module FullAdder(a, b, cin, out, cout);
  72.     input a, b, cin;
  73.     output out, cout;
  74.    
  75.     assign out = a ^ b ^ cin;
  76.     assign cout = a & b | b & cin | a & cin;
  77.  
  78. endmodule
  79.  
  80. module hex_display(IN, OUT);
  81.     input [3:0] IN;
  82.      output reg [7:0] OUT;
  83.      
  84.      always @(*)
  85.      begin
  86.         case(IN[3:0])
  87.             4'b0000: OUT = 7'b1000000;
  88.             4'b0001: OUT = 7'b1111001;
  89.             4'b0010: OUT = 7'b0100100;
  90.             4'b0011: OUT = 7'b0110000;
  91.             4'b0100: OUT = 7'b0011001;
  92.             4'b0101: OUT = 7'b0010010;
  93.             4'b0110: OUT = 7'b0000010;
  94.             4'b0111: OUT = 7'b1111000;
  95.             4'b1000: OUT = 7'b0000000;
  96.             4'b1001: OUT = 7'b0011000;
  97.             4'b1010: OUT = 7'b0001000;
  98.             4'b1011: OUT = 7'b0000011;
  99.             4'b1100: OUT = 7'b1000110;
  100.             4'b1101: OUT = 7'b0100001;
  101.             4'b1110: OUT = 7'b0000110;
  102.             4'b1111: OUT = 7'b0001110;
  103.            
  104.             default: OUT = 7'b0111111;
  105.         endcase
  106.  
  107.     end
  108. endmodule
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