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  1. firmware/target/arm/as3525/ata_sd_as3525.c | 16 ++++++++++++----
  2. firmware/target/arm/as3525/clock-target.h | 6 +++---
  3. firmware/target/arm/as3525/debug-as3525.c | 10 +++++-----
  4. 3 files changed, 20 insertions(+), 12 deletions(-)
  5.  
  6.  
  7. diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c
  8. index 65df027..975df87 100644
  9. --- a/firmware/target/arm/as3525/ata_sd_as3525.c
  10. +++ b/firmware/target/arm/as3525/ata_sd_as3525.c
  11. @@ -103,9 +103,17 @@ static void init_pl180_controller(const int drive);
  12.  
  13. static tCardInfo card_info[NUM_DRIVES];
  14.  
  15. +#ifdef HAVE_MULTIDRIVE
  16. +/* maximum timeouts recommanded in the SD Specification v2.00 */
  17. +#define SD_MAX_READ_TIMEOUT (((drive == SD_SLOT_AS3525)? (AS3525_PCLK_FREQ): \
  18. + (AS3525_IDE_FREQ)) / 1000 * 100) /* 100 ms */
  19. +#define SD_MAX_WRITE_TIMEOUT (((drive == SD_SLOT_AS3525)? (AS3525_PCLK_FREQ): \
  20. + (AS3525_IDE_FREQ)) / 1000 * 250) /* 250 ms */
  21. +#else
  22. /* maximum timeouts recommanded in the SD Specification v2.00 */
  23. -#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
  24. -#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
  25. +#define SD_MAX_READ_TIMEOUT ((AS3525_IDE_FREQ) / 1000 * 100) /* 100 ms */
  26. +#define SD_MAX_WRITE_TIMEOUT ((AS3525_IDE_FREQ) / 1000 * 250) /* 250 ms */
  27. +#endif
  28.  
  29. /* for compatibility */
  30. static long last_disk_activity = -1;
  31. @@ -306,7 +314,7 @@ static int sd_init_card(const int drive)
  32. /* End of Card Identification Mode ************************************/
  33.  
  34.  
  35. - /* full speed for controller clock MCICLK = MCLK = PCLK = 62 MHz */
  36. + /* full speed for controller clock MCICLK = MCLK = PCLK = IDECLK = 62 MHz */
  37. MCI_CLOCK(drive) |= MCI_CLOCK_BYPASS; /* FIXME: 50 MHz is spec limit */
  38. mci_delay();
  39.  
  40. @@ -612,7 +620,7 @@ static int sd_select_bank(signed char bank)
  41. DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
  42. NULL);
  43.  
  44. - MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
  45. + MCI_DATA_TIMER(INTERNAL_AS3525) = ((AS3525_IDE_FREQ) / 1000 * 250) /* 250 ms */;
  46. MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
  47. MCI_DATA_CTRL(INTERNAL_AS3525) = (1<<0) /* enable */ |
  48. (0<<1) /* transfer direction */ |
  49. diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
  50. index 560e067..bf68ea6 100644
  51. --- a/firmware/target/arm/as3525/clock-target.h
  52. +++ b/firmware/target/arm/as3525/clock-target.h
  53. @@ -113,14 +113,14 @@
  54. #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
  55. #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
  56. #define AS3525_I2C_FREQ 400000
  57. +
  58. + /* For now use same divider for ident frequencies on both internal and uSD cards */
  59. #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
  60. #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
  61.  
  62. #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
  63. #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
  64. -#define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq
  65. - but sd transfers fail on some
  66. - players with this limit */
  67. +#define AS3525_IDE_FREQ AS3525_PCLK_FREQ /* The OF uses 66MHz maximal freq */
  68.  
  69. //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */
  70. //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/
  71. diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c
  72. index d8d3e01..4775278 100644
  73. --- a/firmware/target/arm/as3525/debug-as3525.c
  74. +++ b/firmware/target/arm/as3525/debug-as3525.c
  75. @@ -183,9 +183,9 @@ int calc_freq(int clk)
  76. if(!(MCI_NAND & (1<<8)))
  77. return 0;
  78. else if(MCI_NAND & (1<<10))
  79. - return calc_freq(CLK_PCLK);
  80. + return calc_freq(CLK_IDE);
  81. else
  82. - return calc_freq(CLK_PCLK)/(((MCI_NAND & 0xff)+1)*2);
  83. + return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
  84. case CLK_SD_MCLK_MSD:
  85. if(!(MCI_SD & (1<<8)))
  86. return 0;
  87. @@ -222,7 +222,7 @@ bool __dbg_hw_info(void)
  88. {
  89. int line;
  90. int last_nand = 0;
  91. -#if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
  92. +#ifdef HAVE_MULTIDRIVE
  93. int last_sd = 0;
  94. #endif
  95.  
  96. @@ -293,10 +293,10 @@ bool __dbg_hw_info(void)
  97. last_nand = MCI_NAND;
  98. /* MCLK == PCLK */
  99. lcd_putsf(0, line++, "SD :%3dMHz %3dMHz",
  100. - ((last_nand ? (AS3525_PCLK_FREQ/ 1000000): 0) /
  101. + ((last_nand ? (AS3525_IDE_FREQ/ 1000000): 0) /
  102. ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))),
  103. calc_freq(CLK_SD_MCLK_NAND)/1000000);
  104. -#if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2)
  105. +#ifdef HAVE_MULTIDRIVE
  106. if(MCI_SD)
  107. last_sd = MCI_SD;
  108. lcd_putsf(0, line++, "uSD :%3dMHz %3dMHz",
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