library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY primitiv IS PORT(
	a: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	b: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	r: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	cin: IN STD_LOGIC;
	cout: OUT STD_LOGIC;
	oper: IN STD_LOGIC
);
END primitiv;

ARCHITECTURE arch OF primitiv IS

signal I: std_logic_vector(3 downto 0);

BEGIN

komplement: ENTITY WORK.b1kompl port map(b(1 downto 0),i(1 downto 0));
demultipleksor: ENTITY WORK.dmux port map(b(1 downto 0),i(1 downto 0),oper,i(3 downto 2));
fulladder: ENTITY WORK.FA port map(a(1 downto 0),i(3 downto 2),cin,r(1 downto 0),cout );
END arch;