API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Dec 31st, 2019
212
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 247.69 KB | None | 0 0
raw download clone embed print report
  1. ****** START compiling CoreLab.Program:Caller() (MethodHash=4dbcbd65)
  2. Generating code for Windows x64
  3. OPTIONS: compCodeOpt = BLENDED_CODE
  4. OPTIONS: compDbgCode = true
  5. OPTIONS: compDbgInfo = true
  6. OPTIONS: compDbgEnC = false
  7. OPTIONS: compProcedureSplitting = false
  8. OPTIONS: compProcedureSplittingEH = false
  9. IL to import:
  10. IL_0000 00 nop
  11. IL_0001 28 03 00 00 06 call 0x6000003
  12. IL_0006 26 pop
  13. IL_0007 2a ret
  14.  
  15. lvaGrabTemp returning 0 (V00 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
  16. ; Initial local variable assignments
  17. ;
  18. ; V00 OutArgs lclBlk (na) "OutgoingArgSpace"
  19. *************** In compInitDebuggingInfo() for CoreLab.Program:Caller()
  20. getVars() returned cVars = 0, extendOthers = true
  21. info.compStmtOffsetsCount = 0
  22. info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
  23. *************** In fgFindBasicBlocks() for CoreLab.Program:Caller()
  24. Jump targets:
  25. none
  26. New Basic Block BB01 [0000] created.
  27. BB01 [000..008)
  28. CLFLG_MINOPT set for method CoreLab.Program:Caller()
  29. IL Code Size,Instr 8, 4, Basic Block count 1, Local Variable Num,Ref count 1, 0 for method CoreLab.Program:Caller()
  30. IL Code Size,Instr 8, 4, Basic Block count 1, Local Variable Num,Ref count 1, 0 for method CoreLab.Program:Caller()
  31. OPTIONS: opts.MinOpts() == true
  32. Basic block list for 'CoreLab.Program:Caller()'
  33.  
  34. -----------------------------------------------------------------------------------------------------------------------------------------
  35. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  36. -----------------------------------------------------------------------------------------------------------------------------------------
  37. BB01 [0000] 1 1 [000..008) (return)
  38. -----------------------------------------------------------------------------------------------------------------------------------------
  39. *************** In impImport() for CoreLab.Program:Caller()
  40.  
  41. impImportBlockPending for BB01
  42.  
  43. Importing BB01 (PC=000) of 'CoreLab.Program:Caller()'
  44. [ 0] 0 (0x000) nop
  45.  
  46. STMT00000 (IL 0x000... ???)
  47. [000000] ------------ * NO_OP void
  48.  
  49. [ 0] 1 (0x001) call 06000003
  50. In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
  51. HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Double
  52. Found type Hardware Intrinsic SIMD Vector128<double>
  53.  
  54. lvaGrabTemp returning 1 (V01 tmp1) called for impSpillStackEnsure.
  55. Known type Vector128<double>
  56.  
  57.  
  58. STMT00001 (IL 0x001... ???)
  59. [000001] S-C-G------- * CALL void CoreLab.Program.Callee
  60. [000003] ------------ arg0 \--* ADDR byref
  61. [000002] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  62.  
  63. [ 1] 6 (0x006) pop
  64. ... CEE_POP struct ...
  65. [000004] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  66.  
  67. ... optimized to ...
  68. [000005] ------------ * ADDR byref
  69. [000004] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  70.  
  71.  
  72. STMT00002 (IL 0x006... ???)
  73. [000007] ------------ * COMMA void
  74. [000005] ------------ +--* ADDR byref
  75. [000004] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  76. [000006] ------------ \--* NOP void
  77.  
  78. [ 0] 7 (0x007) ret
  79.  
  80. STMT00003 (IL 0x007... ???)
  81. [000008] ------------ * RETURN void
  82.  
  83. *************** in fgTransformIndirectCalls(root)
  84. -- no candidates to transform
  85.  
  86. New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
  87. *************** In fgMorph()
  88. *************** In fgDebugCheckBBlist
  89. *************** In Allocate Objects
  90. Trees before Allocate Objects
  91.  
  92. -----------------------------------------------------------------------------------------------------------------------------------------
  93. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  94. -----------------------------------------------------------------------------------------------------------------------------------------
  95. BB01 [0000] 1 1 [000..008) (return) i
  96. -----------------------------------------------------------------------------------------------------------------------------------------
  97.  
  98. ------------ BB01 [000..008) (return), preds={} succs={}
  99.  
  100. ***** BB01
  101. STMT00000 (IL 0x000...0x000)
  102. [000000] ------------ * NO_OP void
  103.  
  104. ***** BB01
  105. STMT00001 (IL 0x001...0x006)
  106. [000001] S-C-G------- * CALL void CoreLab.Program.Callee
  107. [000003] ------------ arg0 \--* ADDR byref
  108. [000002] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  109.  
  110. ***** BB01
  111. STMT00002 (IL 0x006... ???)
  112. [000007] ------------ * COMMA void
  113. [000005] ------------ +--* ADDR byref
  114. [000004] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  115. [000006] ------------ \--* NOP void
  116.  
  117. ***** BB01
  118. STMT00003 (IL 0x007...0x007)
  119. [000008] ------------ * RETURN void
  120.  
  121. -------------------------------------------------------------------------------------------------------------------
  122.  
  123. *** ObjectAllocationPhase: no newobjs in this method; punting
  124. *************** Exiting Allocate Objects
  125. Trees after Allocate Objects
  126.  
  127. -----------------------------------------------------------------------------------------------------------------------------------------
  128. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  129. -----------------------------------------------------------------------------------------------------------------------------------------
  130. BB01 [0000] 1 1 [000..008) (return) i
  131. -----------------------------------------------------------------------------------------------------------------------------------------
  132.  
  133. ------------ BB01 [000..008) (return), preds={} succs={}
  134.  
  135. ***** BB01
  136. STMT00000 (IL 0x000...0x000)
  137. [000000] ------------ * NO_OP void
  138.  
  139. ***** BB01
  140. STMT00001 (IL 0x001...0x006)
  141. [000001] S-C-G------- * CALL void CoreLab.Program.Callee
  142. [000003] ------------ arg0 \--* ADDR byref
  143. [000002] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  144.  
  145. ***** BB01
  146. STMT00002 (IL 0x006... ???)
  147. [000007] ------------ * COMMA void
  148. [000005] ------------ +--* ADDR byref
  149. [000004] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  150. [000006] ------------ \--* NOP void
  151.  
  152. ***** BB01
  153. STMT00003 (IL 0x007...0x007)
  154. [000008] ------------ * RETURN void
  155.  
  156. -------------------------------------------------------------------------------------------------------------------
  157. New Basic Block BB02 [0001] created.
  158. New scratch BB02
  159.  
  160. *************** After fgAddInternal()
  161.  
  162. -----------------------------------------------------------------------------------------------------------------------------------------
  163. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  164. -----------------------------------------------------------------------------------------------------------------------------------------
  165. BB02 [0001] 1 1 [???..???) i internal
  166. BB01 [0000] 1 1 [000..008) (return) i
  167. -----------------------------------------------------------------------------------------------------------------------------------------
  168.  
  169. *************** Exception Handling table is empty
  170. *************** In fgDebugCheckBBlist
  171.  
  172. *************** In fgRemoveEmptyTry()
  173. No EH in this method, nothing to remove.
  174.  
  175. *************** In fgRemoveEmptyFinally()
  176. No EH in this method, nothing to remove.
  177.  
  178. *************** In fgMergeFinallyChains()
  179. No EH in this method, nothing to merge.
  180.  
  181. *************** In fgCloneFinally()
  182. No EH in this method, no cloning.
  183.  
  184. *************** In fgResetImplicitByRefRefCount()
  185. *************** In fgPromoteStructs()
  186. promotion opt flag not enabled
  187.  
  188. *************** In fgMarkAddressExposedLocals()
  189. LocalAddressVisitor visiting statement:
  190. STMT00004 (IL ???... ???)
  191. [000016] --C-G------- * QMARK void
  192. [000012] Q----------- if +--* EQ int
  193. [000010] ------------ | +--* IND int
  194. [000009] ------------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  195. [000011] ------------ | \--* CNS_INT int 0
  196. [000015] --C-G------- if \--* COLON void
  197. [000013] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  198. [000014] ------------ then \--* NOP void
  199.  
  200. LocalAddressVisitor visiting statement:
  201. STMT00000 (IL 0x000...0x000)
  202. [000000] ------------ * NO_OP void
  203.  
  204. LocalAddressVisitor visiting statement:
  205. STMT00001 (IL 0x001...0x006)
  206. [000001] S-C-G------- * CALL void CoreLab.Program.Callee
  207. [000003] ------------ arg0 \--* ADDR byref
  208. [000002] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 tmp1
  209.  
  210. Local V01 should not be enregistered because: it is address exposed
  211. LocalAddressVisitor modified statement:
  212. STMT00001 (IL 0x001...0x006)
  213. [000001] S-C-G------- * CALL void CoreLab.Program.Callee
  214. [000003] ------------ arg0 \--* LCL_VAR_ADDR byref V01 tmp1
  215.  
  216. LocalAddressVisitor visiting statement:
  217. STMT00002 (IL 0x006... ???)
  218. [000007] ------------ * COMMA void
  219. [000005] ------------ +--* ADDR byref
  220. [000004] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  221. [000006] ------------ \--* NOP void
  222.  
  223. Local V01 should not be enregistered because: it is address exposed
  224.  
  225. LocalAddressVisitor visiting statement:
  226. STMT00003 (IL 0x007...0x007)
  227. [000008] ------------ * RETURN void
  228.  
  229.  
  230. *************** In fgRetypeImplicitByRefArgs()
  231.  
  232. *************** In fgMorphBlocks()
  233.  
  234. Morphing BB02 of 'CoreLab.Program:Caller()'
  235.  
  236. fgMorphTree BB02, STMT00004 (before)
  237. [000016] --C-G------- * QMARK void
  238. [000012] Q----------- if +--* EQ int
  239. [000010] ------------ | +--* IND int
  240. [000009] ------------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  241. [000011] ------------ | \--* CNS_INT int 0
  242. [000015] --C-G------- if \--* COLON void
  243. [000013] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  244. [000014] ------------ then \--* NOP void
  245. Initializing arg info for 13.CALL:
  246. ArgTable for 13.CALL after fgInitArgInfo:
  247.  
  248. Morphing args for 13.CALL:
  249. argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
  250. ArgTable for 13.CALL after fgMorphArgs:
  251.  
  252.  
  253. Morphing BB01 of 'CoreLab.Program:Caller()'
  254.  
  255. fgMorphTree BB01, STMT00000 (before)
  256. [000000] ------------ * NO_OP void
  257.  
  258. fgMorphTree BB01, STMT00001 (before)
  259. [000001] S-C-G------- * CALL void CoreLab.Program.Callee
  260. [000003] ------------ arg0 \--* LCL_VAR_ADDR byref V01 tmp1
  261. Initializing arg info for 1.CALL:
  262. ArgTable for 1.CALL after fgInitArgInfo:
  263. fgArgTabEntry[arg 0 3.LCL_VAR_ADDR long, 1 reg: rcx, align=1]
  264.  
  265. Morphing args for 1.CALL:
  266. argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
  267.  
  268. Sorting the arguments:
  269. Deferred argument ('rcx'):
  270. [000003] -----+------ * LCL_VAR_ADDR long V01 tmp1
  271. Replaced with placeholder node:
  272. [000017] ----------L- * ARGPLACE long
  273.  
  274. Shuffled argument table: rcx
  275. ArgTable for 1.CALL after fgMorphArgs:
  276. fgArgTabEntry[arg 0 3.LCL_VAR_ADDR long, 1 reg: rcx, align=1, lateArgInx=0, processed]
  277.  
  278.  
  279. fgMorphTree BB01, STMT00001 (after)
  280. [000001] S-CXG+------ * CALL void CoreLab.Program.Callee
  281. [000003] -----+------ arg0 in rcx \--* LCL_VAR_ADDR long V01 tmp1
  282.  
  283. fgMorphTree BB01, STMT00002 (before)
  284. [000007] ------------ * COMMA void
  285. [000005] ------------ +--* ADDR byref
  286. [000004] ------------ | \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]>(AX) V01 tmp1
  287. [000006] ------------ \--* NOP void
  288.  
  289. fgMorphTree BB01, STMT00002 (after)
  290. [000006] -----+------ * NOP void
  291.  
  292. fgMorphTree BB01, STMT00003 (before)
  293. [000008] ------------ * RETURN void
  294.  
  295. Expanding top-level qmark in BB02 (before)
  296.  
  297. -----------------------------------------------------------------------------------------------------------------------------------------
  298. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  299. -----------------------------------------------------------------------------------------------------------------------------------------
  300. BB02 [0001] 1 1 [???..???) i internal
  301. -----------------------------------------------------------------------------------------------------------------------------------------
  302.  
  303. ------------ BB02 [???..???), preds={} succs={BB01}
  304.  
  305. ***** BB02
  306. STMT00004 (IL ???... ???)
  307. [000016] --C-G+------ * QMARK void
  308. [000012] J----+-N---- if +--* EQ int
  309. [000010] n----+------ | +--* IND int
  310. [000009] -----+------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  311. [000011] -----+------ | \--* CNS_INT int 0
  312. [000015] --C-G+?----- if \--* COLON void
  313. [000013] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  314. [000014] -----+?----- then \--* NOP void
  315.  
  316. -------------------------------------------------------------------------------------------------------------------
  317. New Basic Block BB03 [0002] created.
  318. BB01 previous predecessor was BB02, now is BB03
  319. New Basic Block BB04 [0003] created.
  320. New Basic Block BB05 [0004] created.
  321.  
  322. Removing statement STMT00004 (IL ???... ???)
  323. [000016] --C-G+------ * QMARK void
  324. [000012] J----+-N---- if +--* EQ int
  325. [000010] n----+------ | +--* IND int
  326. [000009] -----+------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  327. [000011] -----+------ | \--* CNS_INT int 0
  328. [000015] --C-G+?----- if \--* COLON void
  329. [000013] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  330. [000014] -----+?----- then \--* NOP void
  331. in BB02 as useless:
  332.  
  333. BB02 becomes empty
  334.  
  335. Expanding top-level qmark in BB02 (after)
  336.  
  337. -----------------------------------------------------------------------------------------------------------------------------------------
  338. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  339. -----------------------------------------------------------------------------------------------------------------------------------------
  340. BB02 [0001] 1 1 [???..???) i internal
  341. BB04 [0003] 1 1 [???..???)-> BB03 ( cond ) internal
  342. BB05 [0004] 1 0.50 [???..???) internal
  343. BB03 [0002] 2 1 [???..???) i internal label target
  344. -----------------------------------------------------------------------------------------------------------------------------------------
  345.  
  346. ------------ BB02 [???..???), preds={} succs={BB04}
  347.  
  348. ------------ BB04 [???..???) -> BB03 (cond), preds={} succs={BB05,BB03}
  349.  
  350. ***** BB04
  351. STMT00005 (IL ???... ???)
  352. [000018] ------------ * JTRUE void
  353. [000012] J----+-N---- \--* EQ int
  354. [000010] n----+------ +--* IND int
  355. [000009] -----+------ | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  356. [000011] -----+------ \--* CNS_INT int 0
  357.  
  358. ------------ BB05 [???..???), preds={} succs={BB03}
  359.  
  360. ***** BB05
  361. STMT00006 (IL ???... ???)
  362. [000013] --C-G+?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  363.  
  364. ------------ BB03 [???..???), preds={} succs={BB01}
  365.  
  366. -------------------------------------------------------------------------------------------------------------------
  367.  
  368. Renumbering the basic blocks for fgComputePred
  369.  
  370. *************** Before renumbering the basic blocks
  371.  
  372. -----------------------------------------------------------------------------------------------------------------------------------------
  373. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  374. -----------------------------------------------------------------------------------------------------------------------------------------
  375. BB02 [0001] 1 1 [???..???) i internal
  376. BB04 [0003] 1 1 [???..???)-> BB03 ( cond ) internal
  377. BB05 [0004] 1 0.50 [???..???) internal
  378. BB03 [0002] 2 1 [???..???) i internal label target
  379. BB01 [0000] 1 1 [000..008) (return) i gcsafe
  380. -----------------------------------------------------------------------------------------------------------------------------------------
  381.  
  382. *************** Exception Handling table is empty
  383. Renumber BB02 to BB01
  384. Renumber BB04 to BB02
  385. Renumber BB05 to BB03
  386. Renumber BB03 to BB04
  387. Renumber BB01 to BB05
  388.  
  389. *************** After renumbering the basic blocks
  390.  
  391. -----------------------------------------------------------------------------------------------------------------------------------------
  392. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  393. -----------------------------------------------------------------------------------------------------------------------------------------
  394. BB01 [0001] 1 1 [???..???) i internal
  395. BB02 [0003] 1 1 [???..???)-> BB04 ( cond ) internal
  396. BB03 [0004] 1 0.50 [???..???) internal
  397. BB04 [0002] 2 1 [???..???) i internal label target
  398. BB05 [0000] 1 1 [000..008) (return) i gcsafe
  399. -----------------------------------------------------------------------------------------------------------------------------------------
  400.  
  401. *************** Exception Handling table is empty
  402.  
  403. New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short)
  404.  
  405. *************** In fgComputePreds()
  406.  
  407. -----------------------------------------------------------------------------------------------------------------------------------------
  408. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  409. -----------------------------------------------------------------------------------------------------------------------------------------
  410. BB01 [0001] 1 1 [???..???) i internal
  411. BB02 [0003] 1 1 [???..???)-> BB04 ( cond ) internal
  412. BB03 [0004] 1 0.50 [???..???) internal
  413. BB04 [0002] 2 1 [???..???) i internal label target
  414. BB05 [0000] 1 1 [000..008) (return) i gcsafe
  415. -----------------------------------------------------------------------------------------------------------------------------------------
  416.  
  417.  
  418. *************** After fgComputePreds()
  419.  
  420. -----------------------------------------------------------------------------------------------------------------------------------------
  421. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  422. -----------------------------------------------------------------------------------------------------------------------------------------
  423. BB01 [0001] 1 1 [???..???) i internal label target
  424. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  425. BB03 [0004] 1 BB02 0.50 [???..???) internal
  426. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  427. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  428. -----------------------------------------------------------------------------------------------------------------------------------------
  429.  
  430. *************** In fgComputeBlockAndEdgeWeights()
  431.  
  432. -----------------------------------------------------------------------------------------------------------------------------------------
  433. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  434. -----------------------------------------------------------------------------------------------------------------------------------------
  435. BB01 [0001] 1 1 [???..???) i internal label target
  436. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  437. BB03 [0004] 1 BB02 0.50 [???..???) internal
  438. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  439. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  440. -----------------------------------------------------------------------------------------------------------------------------------------
  441.  
  442. -- no profile data, so using default called count
  443. -- not optimizing, so not computing edge weights
  444. *************** In fgCreateFunclets()
  445.  
  446. After fgCreateFunclets()
  447. -----------------------------------------------------------------------------------------------------------------------------------------
  448. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  449. -----------------------------------------------------------------------------------------------------------------------------------------
  450. BB01 [0001] 1 1 [???..???) i internal label target
  451. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  452. BB03 [0004] 1 BB02 0.50 [???..???) internal
  453. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  454. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  455. -----------------------------------------------------------------------------------------------------------------------------------------
  456.  
  457. *************** Exception Handling table is empty
  458. *************** In fgDebugCheckBBlist
  459.  
  460. *************** In lvaMarkLocalVars()
  461. *** lvaComputeRefCounts ***
  462. *************** In fgFindOperOrder()
  463. *************** In fgSetBlockOrder()
  464. The biggest BB has 5 tree nodes
  465.  
  466. -----------------------------------------------------------------------------------------------------------------------------------------
  467. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  468. -----------------------------------------------------------------------------------------------------------------------------------------
  469. BB01 [0001] 1 1 [???..???) i internal label target
  470. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  471. BB03 [0004] 1 BB02 0.50 [???..???) internal
  472. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  473. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  474. -----------------------------------------------------------------------------------------------------------------------------------------
  475.  
  476. ------------ BB01 [???..???), preds={} succs={BB02}
  477.  
  478. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  479.  
  480. ***** BB02
  481. STMT00005 (IL ???... ???)
  482. N005 ( 9, 16) [000018] ------------ * JTRUE void
  483. N004 ( 7, 14) [000012] J------N---- \--* EQ int
  484. N002 ( 5, 12) [000010] n----------- +--* IND int
  485. N001 ( 3, 10) [000009] ------------ | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  486. N003 ( 1, 1) [000011] ------------ \--* CNS_INT int 0
  487.  
  488. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  489.  
  490. ***** BB03
  491. STMT00006 (IL ???... ???)
  492. N001 ( 14, 5) [000013] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  493.  
  494. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  495.  
  496. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  497.  
  498. ***** BB05
  499. STMT00000 (IL 0x000...0x000)
  500. N001 ( 1, 1) [000000] ------------ * NO_OP void
  501.  
  502. ***** BB05
  503. STMT00001 (IL 0x001...0x006)
  504. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  505. N002 ( 3, 3) [000003] ------------ arg0 in rcx \--* LCL_VAR_ADDR long V01 tmp1
  506.  
  507. ***** BB05
  508. STMT00002 (IL 0x006... ???)
  509. N001 ( 0, 0) [000006] ------------ * NOP void
  510.  
  511. ***** BB05
  512. STMT00003 (IL 0x007...0x007)
  513. N001 ( 0, 0) [000008] ------------ * RETURN void
  514.  
  515. -------------------------------------------------------------------------------------------------------------------
  516.  
  517.  
  518. *************** In fgDetermineFirstColdBlock()
  519. No procedure splitting will be done for this method
  520. *************** In IR Rationalize
  521. Trees before IR Rationalize
  522.  
  523. -----------------------------------------------------------------------------------------------------------------------------------------
  524. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  525. -----------------------------------------------------------------------------------------------------------------------------------------
  526. BB01 [0001] 1 1 [???..???) i internal label target
  527. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  528. BB03 [0004] 1 BB02 0.50 [???..???) internal
  529. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target
  530. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe
  531. -----------------------------------------------------------------------------------------------------------------------------------------
  532.  
  533. ------------ BB01 [???..???), preds={} succs={BB02}
  534.  
  535. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  536.  
  537. ***** BB02
  538. STMT00005 (IL ???... ???)
  539. N005 ( 9, 16) [000018] ------------ * JTRUE void
  540. N004 ( 7, 14) [000012] J------N---- \--* EQ int
  541. N002 ( 5, 12) [000010] n----------- +--* IND int
  542. N001 ( 3, 10) [000009] ------------ | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  543. N003 ( 1, 1) [000011] ------------ \--* CNS_INT int 0
  544.  
  545. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  546.  
  547. ***** BB03
  548. STMT00006 (IL ???... ???)
  549. N001 ( 14, 5) [000013] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  550.  
  551. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  552.  
  553. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  554.  
  555. ***** BB05
  556. STMT00000 (IL 0x000...0x000)
  557. N001 ( 1, 1) [000000] ------------ * NO_OP void
  558.  
  559. ***** BB05
  560. STMT00001 (IL 0x001...0x006)
  561. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  562. N002 ( 3, 3) [000003] ------------ arg0 in rcx \--* LCL_VAR_ADDR long V01 tmp1
  563.  
  564. ***** BB05
  565. STMT00002 (IL 0x006... ???)
  566. N001 ( 0, 0) [000006] ------------ * NOP void
  567.  
  568. ***** BB05
  569. STMT00003 (IL 0x007...0x007)
  570. N001 ( 0, 0) [000008] ------------ * RETURN void
  571.  
  572. -------------------------------------------------------------------------------------------------------------------
  573. *************** Exiting IR Rationalize
  574. Trees after IR Rationalize
  575.  
  576. -----------------------------------------------------------------------------------------------------------------------------------------
  577. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  578. -----------------------------------------------------------------------------------------------------------------------------------------
  579. BB01 [0001] 1 1 [???..???) i internal label target LIR
  580. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  581. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  582. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  583. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  584. -----------------------------------------------------------------------------------------------------------------------------------------
  585.  
  586. ------------ BB01 [???..???), preds={} succs={BB02}
  587.  
  588. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  589. N001 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0x7fff50fbeaf0 token
  590. /--* t9 long
  591. N002 ( 5, 12) [000010] n----------- t10 = * IND int
  592. N003 ( 1, 1) [000011] ------------ t11 = CNS_INT int 0
  593. /--* t10 int
  594. +--* t11 int
  595. N004 ( 7, 14) [000012] J------N---- t12 = * EQ int
  596. /--* t12 int
  597. N005 ( 9, 16) [000018] ------------ * JTRUE void
  598.  
  599. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  600. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  601.  
  602. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  603.  
  604. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  605. [000019] ------------ IL_OFFSET void IL offset: 0x0
  606. N001 ( 1, 1) [000000] ------------ NO_OP void
  607. [000020] ------------ IL_OFFSET void IL offset: 0x1
  608. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  609. /--* t3 long arg0 in rcx
  610. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  611. [000021] ------------ IL_OFFSET void IL offset: 0x6
  612. N001 ( 0, 0) [000006] ------------ NOP void
  613. [000022] ------------ IL_OFFSET void IL offset: 0x7
  614. N001 ( 0, 0) [000008] ------------ RETURN void
  615.  
  616. -------------------------------------------------------------------------------------------------------------------
  617. *************** In fgDebugCheckBBlist
  618. Bumping outgoingArgSpaceSize to 32 for call [000013]
  619. outgoingArgSpaceSize 32 sufficient for call [000001], which needs 32
  620. *************** In fgDebugCheckBBlist
  621. *************** In Lowering
  622. Trees before Lowering
  623.  
  624. -----------------------------------------------------------------------------------------------------------------------------------------
  625. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  626. -----------------------------------------------------------------------------------------------------------------------------------------
  627. BB01 [0001] 1 1 [???..???) i internal label target LIR
  628. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  629. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  630. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  631. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  632. -----------------------------------------------------------------------------------------------------------------------------------------
  633.  
  634. ------------ BB01 [???..???), preds={} succs={BB02}
  635.  
  636. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  637. N001 ( 3, 10) [000009] ------------ t9 = CNS_INT(h) long 0x7fff50fbeaf0 token
  638. /--* t9 long
  639. N002 ( 5, 12) [000010] n----------- t10 = * IND int
  640. N003 ( 1, 1) [000011] ------------ t11 = CNS_INT int 0
  641. /--* t10 int
  642. +--* t11 int
  643. N004 ( 7, 14) [000012] J------N---- t12 = * EQ int
  644. /--* t12 int
  645. N005 ( 9, 16) [000018] ------------ * JTRUE void
  646.  
  647. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  648. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  649.  
  650. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  651.  
  652. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  653. [000019] ------------ IL_OFFSET void IL offset: 0x0
  654. N001 ( 1, 1) [000000] ------------ NO_OP void
  655. [000020] ------------ IL_OFFSET void IL offset: 0x1
  656. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  657. /--* t3 long arg0 in rcx
  658. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  659. [000021] ------------ IL_OFFSET void IL offset: 0x6
  660. N001 ( 0, 0) [000006] ------------ NOP void
  661. [000022] ------------ IL_OFFSET void IL offset: 0x7
  662. N001 ( 0, 0) [000008] ------------ RETURN void
  663.  
  664. -------------------------------------------------------------------------------------------------------------------
  665. lowering call (before):
  666. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  667.  
  668. objp:
  669. ======
  670.  
  671. args:
  672. ======
  673.  
  674. late:
  675. ======
  676. lowering call (after):
  677. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  678.  
  679. lowering call (before):
  680. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  681. /--* t3 long arg0 in rcx
  682. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  683.  
  684. objp:
  685. ======
  686.  
  687. args:
  688. ======
  689. lowering arg : N001 ( 0, 0) [000017] ----------L- * ARGPLACE long
  690.  
  691. late:
  692. ======
  693. lowering arg : N002 ( 3, 3) [000003] ------------ * LCL_VAR_ADDR long V01 tmp1
  694. new node is : [000023] ------------ * PUTARG_REG long REG rcx
  695.  
  696. lowering call (after):
  697. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  698. /--* t3 long
  699. [000023] ------------ t23 = * PUTARG_REG long REG rcx
  700. /--* t23 long arg0 in rcx
  701. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  702.  
  703. lowering GT_RETURN
  704. N001 ( 0, 0) [000008] ------------ * RETURN void
  705. ============Lower has completed modifying nodes.
  706.  
  707. -----------------------------------------------------------------------------------------------------------------------------------------
  708. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  709. -----------------------------------------------------------------------------------------------------------------------------------------
  710. BB01 [0001] 1 1 [???..???) i internal label target LIR
  711. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  712. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  713. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  714. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  715. -----------------------------------------------------------------------------------------------------------------------------------------
  716.  
  717. ------------ BB01 [???..???), preds={} succs={BB02}
  718.  
  719. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  720. N001 ( 3, 10) [000009] -c---------- t9 = CNS_INT(h) long 0x7fff50fbeaf0 token
  721. /--* t9 long
  722. N002 ( 5, 12) [000010] nc---------- t10 = * IND int
  723. N003 ( 1, 1) [000011] -c---------- t11 = CNS_INT int 0
  724. /--* t10 int
  725. +--* t11 int
  726. N004 ( 7, 14) [000012] J------N---- * EQ void
  727. N005 ( 9, 16) [000018] ------------ * JTRUE void
  728.  
  729. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  730. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  731.  
  732. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  733.  
  734. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  735. [000019] ------------ IL_OFFSET void IL offset: 0x0
  736. N001 ( 1, 1) [000000] ------------ NO_OP void
  737. [000020] ------------ IL_OFFSET void IL offset: 0x1
  738. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  739. /--* t3 long
  740. [000023] ------------ t23 = * PUTARG_REG long REG rcx
  741. /--* t23 long arg0 in rcx
  742. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  743. [000021] ------------ IL_OFFSET void IL offset: 0x6
  744. N001 ( 0, 0) [000006] ------------ NOP void
  745. [000022] ------------ IL_OFFSET void IL offset: 0x7
  746. N001 ( 0, 0) [000008] ------------ RETURN void
  747.  
  748. -------------------------------------------------------------------------------------------------------------------
  749.  
  750. *** lvaComputeRefCounts ***
  751. *************** In fgLocalVarLiveness()
  752. ; Initial local variable assignments
  753. ;
  754. ; V00 OutArgs lclBlk (32) "OutgoingArgSpace"
  755. ; V01 tmp1 simd16 do-not-enreg[XS] addr-exposed "impSpillStackEnsure"
  756. In fgLocalVarLivenessInit
  757. *************** In fgPerBlockLocalVarLiveness()
  758. *************** In fgInterBlockLocalVarLiveness()
  759.  
  760. *** lvaComputeRefCounts ***
  761. Liveness pass finished after lowering, IR:
  762.  
  763. -----------------------------------------------------------------------------------------------------------------------------------------
  764. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  765. -----------------------------------------------------------------------------------------------------------------------------------------
  766. BB01 [0001] 1 1 [???..???) i internal label target LIR
  767. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  768. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  769. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  770. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  771. -----------------------------------------------------------------------------------------------------------------------------------------
  772.  
  773. ------------ BB01 [???..???), preds={} succs={BB02}
  774.  
  775. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  776. N001 ( 3, 10) [000009] -c---------- t9 = CNS_INT(h) long 0x7fff50fbeaf0 token
  777. /--* t9 long
  778. N002 ( 5, 12) [000010] nc---------- t10 = * IND int
  779. N003 ( 1, 1) [000011] -c---------- t11 = CNS_INT int 0
  780. /--* t10 int
  781. +--* t11 int
  782. N004 ( 7, 14) [000012] J------N---- * EQ void
  783. N005 ( 9, 16) [000018] ------------ * JTRUE void
  784.  
  785. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  786. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  787.  
  788. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  789.  
  790. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  791. [000019] ------------ IL_OFFSET void IL offset: 0x0
  792. N001 ( 1, 1) [000000] ------------ NO_OP void
  793. [000020] ------------ IL_OFFSET void IL offset: 0x1
  794. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  795. /--* t3 long
  796. [000023] ------------ t23 = * PUTARG_REG long REG rcx
  797. /--* t23 long arg0 in rcx
  798. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  799. [000021] ------------ IL_OFFSET void IL offset: 0x6
  800. N001 ( 0, 0) [000006] ------------ NOP void
  801. [000022] ------------ IL_OFFSET void IL offset: 0x7
  802. N001 ( 0, 0) [000008] ------------ RETURN void
  803.  
  804. -------------------------------------------------------------------------------------------------------------------
  805. *************** Exiting Lowering
  806. Trees after Lowering
  807.  
  808. -----------------------------------------------------------------------------------------------------------------------------------------
  809. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  810. -----------------------------------------------------------------------------------------------------------------------------------------
  811. BB01 [0001] 1 1 [???..???) i internal label target LIR
  812. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  813. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  814. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  815. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  816. -----------------------------------------------------------------------------------------------------------------------------------------
  817.  
  818. ------------ BB01 [???..???), preds={} succs={BB02}
  819.  
  820. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  821. N001 ( 3, 10) [000009] -c---------- t9 = CNS_INT(h) long 0x7fff50fbeaf0 token
  822. /--* t9 long
  823. N002 ( 5, 12) [000010] nc---------- t10 = * IND int
  824. N003 ( 1, 1) [000011] -c---------- t11 = CNS_INT int 0
  825. /--* t10 int
  826. +--* t11 int
  827. N004 ( 7, 14) [000012] J------N---- * EQ void
  828. N005 ( 9, 16) [000018] ------------ * JTRUE void
  829.  
  830. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  831. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  832.  
  833. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  834.  
  835. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  836. [000019] ------------ IL_OFFSET void IL offset: 0x0
  837. N001 ( 1, 1) [000000] ------------ NO_OP void
  838. [000020] ------------ IL_OFFSET void IL offset: 0x1
  839. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  840. /--* t3 long
  841. [000023] ------------ t23 = * PUTARG_REG long REG rcx
  842. /--* t23 long arg0 in rcx
  843. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  844. [000021] ------------ IL_OFFSET void IL offset: 0x6
  845. N001 ( 0, 0) [000006] ------------ NOP void
  846. [000022] ------------ IL_OFFSET void IL offset: 0x7
  847. N001 ( 0, 0) [000008] ------------ RETURN void
  848.  
  849. -------------------------------------------------------------------------------------------------------------------
  850. *************** In fgDebugCheckBBlist
  851. *************** In StackLevelSetter
  852. Trees before StackLevelSetter
  853.  
  854. -----------------------------------------------------------------------------------------------------------------------------------------
  855. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  856. -----------------------------------------------------------------------------------------------------------------------------------------
  857. BB01 [0001] 1 1 [???..???) i internal label target LIR
  858. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  859. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  860. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  861. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  862. -----------------------------------------------------------------------------------------------------------------------------------------
  863.  
  864. ------------ BB01 [???..???), preds={} succs={BB02}
  865.  
  866. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  867. N001 ( 3, 10) [000009] -c---------- t9 = CNS_INT(h) long 0x7fff50fbeaf0 token
  868. /--* t9 long
  869. N002 ( 5, 12) [000010] nc---------- t10 = * IND int
  870. N003 ( 1, 1) [000011] -c---------- t11 = CNS_INT int 0
  871. /--* t10 int
  872. +--* t11 int
  873. N004 ( 7, 14) [000012] J------N---- * EQ void
  874. N005 ( 9, 16) [000018] ------------ * JTRUE void
  875.  
  876. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  877. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  878.  
  879. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  880.  
  881. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  882. [000019] ------------ IL_OFFSET void IL offset: 0x0
  883. N001 ( 1, 1) [000000] ------------ NO_OP void
  884. [000020] ------------ IL_OFFSET void IL offset: 0x1
  885. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  886. /--* t3 long
  887. [000023] ------------ t23 = * PUTARG_REG long REG rcx
  888. /--* t23 long arg0 in rcx
  889. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  890. [000021] ------------ IL_OFFSET void IL offset: 0x6
  891. N001 ( 0, 0) [000006] ------------ NOP void
  892. [000022] ------------ IL_OFFSET void IL offset: 0x7
  893. N001 ( 0, 0) [000008] ------------ RETURN void
  894.  
  895. -------------------------------------------------------------------------------------------------------------------
  896. *************** Exiting StackLevelSetter
  897. Trees after StackLevelSetter
  898.  
  899. -----------------------------------------------------------------------------------------------------------------------------------------
  900. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  901. -----------------------------------------------------------------------------------------------------------------------------------------
  902. BB01 [0001] 1 1 [???..???) i internal label target LIR
  903. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  904. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  905. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  906. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  907. -----------------------------------------------------------------------------------------------------------------------------------------
  908.  
  909. ------------ BB01 [???..???), preds={} succs={BB02}
  910.  
  911. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  912. N001 ( 3, 10) [000009] -c---------- t9 = CNS_INT(h) long 0x7fff50fbeaf0 token
  913. /--* t9 long
  914. N002 ( 5, 12) [000010] nc---------- t10 = * IND int
  915. N003 ( 1, 1) [000011] -c---------- t11 = CNS_INT int 0
  916. /--* t10 int
  917. +--* t11 int
  918. N004 ( 7, 14) [000012] J------N---- * EQ void
  919. N005 ( 9, 16) [000018] ------------ * JTRUE void
  920.  
  921. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  922. N001 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  923.  
  924. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  925.  
  926. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  927. [000019] ------------ IL_OFFSET void IL offset: 0x0
  928. N001 ( 1, 1) [000000] ------------ NO_OP void
  929. [000020] ------------ IL_OFFSET void IL offset: 0x1
  930. N002 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1
  931. /--* t3 long
  932. [000023] ------------ t23 = * PUTARG_REG long REG rcx
  933. /--* t23 long arg0 in rcx
  934. N003 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee
  935. [000021] ------------ IL_OFFSET void IL offset: 0x6
  936. N001 ( 0, 0) [000006] ------------ NOP void
  937. [000022] ------------ IL_OFFSET void IL offset: 0x7
  938. N001 ( 0, 0) [000008] ------------ RETURN void
  939.  
  940. -------------------------------------------------------------------------------------------------------------------
  941. *************** In fgDebugCheckBBlist
  942. Clearing modified regs.
  943.  
  944. buildIntervals ========
  945.  
  946. -----------------
  947. LIVENESS:
  948. -----------------
  949. BB01 use def in out
  950. {}
  951. {}
  952. {}
  953. {}
  954. BB02 use def in out
  955. {}
  956. {}
  957. {}
  958. {}
  959. BB03 use def in out
  960. {}
  961. {}
  962. {}
  963. {}
  964. BB04 use def in out
  965. {}
  966. {}
  967. {}
  968. {}
  969. BB05 use def in out
  970. {}
  971. {}
  972. {}
  973. {}
  974.  
  975. FP callee save candidate vars: None
  976.  
  977. floatVarCount = 0; hasLoops = 0, singleExit = 1
  978. TUPLE STYLE DUMP BEFORE LSRA
  979. LSRA Block Sequence: BB01( 1 )
  980. BB02( 1 )
  981. BB03( 0.50)
  982. BB04( 1 )
  983. BB05( 1 )
  984.  
  985. BB01 [???..???), preds={} succs={BB02}
  986. =====
  987.  
  988. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  989. =====
  990. N001. CNS_INT(h) 0x7fff50fbeaf0 token
  991. N002. IND
  992. N003. CNS_INT 0
  993. N004. EQ
  994. N005. JTRUE
  995.  
  996. BB03 [???..???), preds={BB02} succs={BB04}
  997. =====
  998. N001. CALL help
  999.  
  1000. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  1001. =====
  1002.  
  1003. BB05 [000..008) (return), preds={BB04} succs={}
  1004. =====
  1005. N000. IL_OFFSET IL offset: 0x0
  1006. N001. NO_OP
  1007. N000. IL_OFFSET IL offset: 0x1
  1008. N002. t3 = LCL_VAR_ADDR V01 tmp1
  1009. N000. t23 = PUTARG_REG; t3
  1010. N003. CALL ; t23
  1011. N000. IL_OFFSET IL offset: 0x6
  1012. N001. NOP
  1013. N000. IL_OFFSET IL offset: 0x7
  1014. N001. RETURN
  1015.  
  1016.  
  1017.  
  1018.  
  1019. buildIntervals second part ========
  1020.  
  1021. NEW BLOCK BB01
  1022. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1023.  
  1024.  
  1025. NEW BLOCK BB02
  1026.  
  1027.  
  1028. Setting BB01 as the predecessor for determining incoming variable registers of BB02
  1029. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1030.  
  1031. DefList: { }
  1032. N004 ( 3, 10) [000009] -c---------- * CNS_INT(h) long 0x7fff50fbeaf0 token REG NA
  1033. Contained
  1034. DefList: { }
  1035. N006 ( 5, 12) [000010] nc---------- * IND int REG NA
  1036. Contained
  1037. DefList: { }
  1038. N008 ( 1, 1) [000011] -c---------- * CNS_INT int 0 REG NA
  1039. Contained
  1040. DefList: { }
  1041. N010 ( 7, 14) [000012] J------N---- * EQ void REG NA
  1042.  
  1043. DefList: { }
  1044. N012 ( 9, 16) [000018] ------------ * JTRUE void REG NA
  1045.  
  1046.  
  1047. NEW BLOCK BB03
  1048.  
  1049.  
  1050. Setting BB02 as the predecessor for determining incoming variable registers of BB03
  1051. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1052.  
  1053. DefList: { }
  1054. N016 ( 14, 5) [000013] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  1055. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1>
  1056. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1>
  1057. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1>
  1058. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1>
  1059. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1>
  1060. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1>
  1061. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1>
  1062. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1>
  1063. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1>
  1064. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1>
  1065. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1>
  1066. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1>
  1067. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1>
  1068.  
  1069.  
  1070. NEW BLOCK BB04
  1071.  
  1072.  
  1073. Setting BB02 as the predecessor for determining incoming variable registers of BB04
  1074. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1075.  
  1076.  
  1077. NEW BLOCK BB05
  1078.  
  1079.  
  1080. Setting BB04 as the predecessor for determining incoming variable registers of BB05
  1081. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1082.  
  1083. DefList: { }
  1084. N022 (???,???) [000019] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
  1085.  
  1086. DefList: { }
  1087. N024 ( 1, 1) [000000] ------------ * NO_OP void REG NA
  1088.  
  1089. DefList: { }
  1090. N026 (???,???) [000020] ------------ * IL_OFFSET void IL offset: 0x1 REG NA
  1091.  
  1092. DefList: { }
  1093. N028 ( 3, 3) [000003] ------------ * LCL_VAR_ADDR long V01 tmp1 NA REG NA
  1094. Interval 0: long RefPositions {} physReg:NA Preferences=[allIntButFP]
  1095. <RefPosition #18 @29 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB05 regmask=[allIntButFP] minReg=1>
  1096.  
  1097. DefList: { N028.t3. LCL_VAR_ADDR }
  1098. N030 (???,???) [000023] ------------ * PUTARG_REG long REG rcx
  1099. <RefPosition #19 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1100. <RefPosition #20 @30 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
  1101. Interval 1: long RefPositions {} physReg:NA Preferences=[allIntButFP]
  1102. <RefPosition #21 @31 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1103. <RefPosition #22 @31 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
  1104.  
  1105. DefList: { N030.t23. PUTARG_REG }
  1106. N032 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee REG NA
  1107. <RefPosition #23 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1108. <RefPosition #24 @32 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
  1109. <RefPosition #25 @33 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1>
  1110. <RefPosition #26 @33 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1111. <RefPosition #27 @33 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1>
  1112. <RefPosition #28 @33 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1>
  1113. <RefPosition #29 @33 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1>
  1114. <RefPosition #30 @33 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1>
  1115. <RefPosition #31 @33 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1>
  1116. <RefPosition #32 @33 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1>
  1117. <RefPosition #33 @33 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1>
  1118. <RefPosition #34 @33 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1>
  1119. <RefPosition #35 @33 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1>
  1120. <RefPosition #36 @33 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1>
  1121. <RefPosition #37 @33 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1>
  1122.  
  1123. DefList: { }
  1124. N034 (???,???) [000021] ------------ * IL_OFFSET void IL offset: 0x6 REG NA
  1125.  
  1126. DefList: { }
  1127. N036 ( 0, 0) [000006] ------------ * NOP void REG NA
  1128.  
  1129. DefList: { }
  1130. N038 (???,???) [000022] ------------ * IL_OFFSET void IL offset: 0x7 REG NA
  1131.  
  1132. DefList: { }
  1133. N040 ( 0, 0) [000008] ------------ * RETURN void REG NA
  1134.  
  1135.  
  1136. Linear scan intervals BEFORE VALIDATING INTERVALS:
  1137. Interval 0: long RefPositions {#18@29 #20@30} physReg:NA Preferences=[rcx]
  1138. Interval 1: long RefPositions {#22@31 #24@32} physReg:NA Preferences=[rcx]
  1139.  
  1140. ------------
  1141. REFPOSITIONS BEFORE VALIDATING INTERVALS:
  1142. ------------
  1143. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1144. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1145. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1146. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  1147. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  1148. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  1149. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  1150. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  1151. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  1152. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  1153. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  1154. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  1155. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  1156. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  1157. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  1158. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  1159. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1160. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1161. <RefPosition #18 @29 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB05 regmask=[rcx] minReg=1>
  1162. <RefPosition #19 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1163. <RefPosition #20 @30 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
  1164. <RefPosition #21 @31 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1165. <RefPosition #22 @31 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
  1166. <RefPosition #23 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1167. <RefPosition #24 @32 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
  1168. <RefPosition #25 @33 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
  1169. <RefPosition #26 @33 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
  1170. <RefPosition #27 @33 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
  1171. <RefPosition #28 @33 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
  1172. <RefPosition #29 @33 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
  1173. <RefPosition #30 @33 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
  1174. <RefPosition #31 @33 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
  1175. <RefPosition #32 @33 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1 last>
  1176. <RefPosition #33 @33 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1 last>
  1177. <RefPosition #34 @33 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1 last>
  1178. <RefPosition #35 @33 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1 last>
  1179. <RefPosition #36 @33 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1 last>
  1180. <RefPosition #37 @33 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1 last>
  1181. TUPLE STYLE DUMP WITH REF POSITIONS
  1182. Incoming Parameters:
  1183. BB01 [???..???), preds={} succs={BB02}
  1184. =====
  1185.  
  1186. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  1187. =====
  1188. N004. CNS_INT(h) 0x7fff50fbeaf0 token
  1189. N006. IND
  1190. N008. CNS_INT 0
  1191. N010. EQ
  1192. N012. JTRUE
  1193.  
  1194. BB03 [???..???), preds={BB02} succs={BB04}
  1195. =====
  1196. N016. CALL help
  1197. Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5
  1198.  
  1199. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  1200. =====
  1201.  
  1202. BB05 [000..008) (return), preds={BB04} succs={}
  1203. =====
  1204. N022. IL_OFFSET IL offset: 0x0
  1205. N024. NO_OP
  1206. N026. IL_OFFSET IL offset: 0x1
  1207. N028. LCL_VAR_ADDR V01 tmp1 NA
  1208. Def:<I0>(#18)
  1209. N030. PUTARG_REG
  1210. Use:<I0>(#20) Fixed:rcx(#19) *
  1211. Def:<I1>(#22) rcx
  1212. N032. CALL
  1213. Use:<I1>(#24) Fixed:rcx(#23) *
  1214. Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5
  1215. N034. IL_OFFSET IL offset: 0x6
  1216. N036. NOP
  1217. N038. IL_OFFSET IL offset: 0x7
  1218. N040. RETURN
  1219.  
  1220.  
  1221.  
  1222.  
  1223. Linear scan intervals after buildIntervals:
  1224. Interval 0: long RefPositions {#18@29 #20@30} physReg:NA Preferences=[rcx]
  1225. Interval 1: long RefPositions {#22@31 #24@32} physReg:NA Preferences=[rcx]
  1226.  
  1227. *************** In LinearScan::allocateRegisters()
  1228.  
  1229. Linear scan intervals before allocateRegisters:
  1230. Interval 0: long RefPositions {#18@29 #20@30} physReg:NA Preferences=[rcx]
  1231. Interval 1: long RefPositions {#22@31 #24@32} physReg:NA Preferences=[rcx]
  1232.  
  1233. ------------
  1234. REFPOSITIONS BEFORE ALLOCATION:
  1235. ------------
  1236. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1237. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1238. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1239. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  1240. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  1241. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  1242. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  1243. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  1244. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  1245. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  1246. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  1247. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  1248. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  1249. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  1250. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  1251. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  1252. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1253. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1254. <RefPosition #18 @29 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB05 regmask=[rcx] minReg=1>
  1255. <RefPosition #19 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1256. <RefPosition #20 @30 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
  1257. <RefPosition #21 @31 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1258. <RefPosition #22 @31 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
  1259. <RefPosition #23 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1260. <RefPosition #24 @32 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
  1261. <RefPosition #25 @33 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
  1262. <RefPosition #26 @33 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
  1263. <RefPosition #27 @33 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
  1264. <RefPosition #28 @33 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
  1265. <RefPosition #29 @33 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
  1266. <RefPosition #30 @33 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
  1267. <RefPosition #31 @33 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
  1268. <RefPosition #32 @33 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1 last>
  1269. <RefPosition #33 @33 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1 last>
  1270. <RefPosition #34 @33 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1 last>
  1271. <RefPosition #35 @33 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1 last>
  1272. <RefPosition #36 @33 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1 last>
  1273. <RefPosition #37 @33 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1 last>
  1274.  
  1275.  
  1276. Allocating Registers
  1277. --------------------
  1278. The following table has one or more rows for each RefPosition that is handled during allocation.
  1279. The first column provides the basic information about the RefPosition, with its type (e.g. Def,
  1280. Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
  1281. action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
  1282. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
  1283. active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
  1284. Columns are only printed up to the last modifed register, which may increase during allocation,
  1285. in which case additional columns will appear.
  1286. Registers which are not marked modified have ---- in their column.
  1287.  
  1288. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1289. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1290. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1291. | | | | | | | | | | | | | | |
  1292. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  1293. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1294. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1295. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1296. 2.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  1297. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1298. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1299. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1300. 14.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  1301. 17.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  1302. 17.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1303. 17.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1304. 17.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1305. 17.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1306. 17.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1307. 17.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1308. 17.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1309. 17.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1310. 17.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1311. 17.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1312. 17.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1313. 17.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1314. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1315. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1316. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1317. 18.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  1318. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1319. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1320. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1321. 20.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  1322. 29.#18 I0 Def Alloc rcx | |I0 a| | | | | | | | | | | | |
  1323. 30.#19 rcx Fixd Keep rcx | |I0 a| | | | | | | | | | | | |
  1324. 30.#20 I0 Use * Keep rcx | |I0 a| | | | | | | | | | | | |
  1325. 31.#21 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
  1326. 31.#22 I1 Def Alloc rcx | |I1 a| | | | | | | | | | | | |
  1327. 32.#23 rcx Fixd Keep rcx | |I1 a| | | | | | | | | | | | |
  1328. 32.#24 I1 Use * Keep rcx | |I1 a| | | | | | | | | | | | |
  1329. 33.#25 rax Kill Keep rax | | | | | | | | | | | | | | |
  1330. 33.#26 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1331. 33.#27 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1332. 33.#28 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1333. 33.#29 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1334. 33.#30 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1335. 33.#31 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1336. 33.#32 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1337. 33.#33 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1338. 33.#34 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1339. 33.#35 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1340. 33.#36 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1341. 33.#37 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1342.  
  1343. ------------
  1344. REFPOSITIONS AFTER ALLOCATION:
  1345. ------------
  1346. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  1347. <RefPosition #1 @2 RefTypeBB BB02 regmask=[] minReg=1>
  1348. <RefPosition #2 @14 RefTypeBB BB03 regmask=[] minReg=1>
  1349. <RefPosition #3 @17 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  1350. <RefPosition #4 @17 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  1351. <RefPosition #5 @17 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  1352. <RefPosition #6 @17 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  1353. <RefPosition #7 @17 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  1354. <RefPosition #8 @17 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  1355. <RefPosition #9 @17 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  1356. <RefPosition #10 @17 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  1357. <RefPosition #11 @17 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  1358. <RefPosition #12 @17 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  1359. <RefPosition #13 @17 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  1360. <RefPosition #14 @17 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  1361. <RefPosition #15 @17 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  1362. <RefPosition #16 @18 RefTypeBB BB04 regmask=[] minReg=1>
  1363. <RefPosition #17 @20 RefTypeBB BB05 regmask=[] minReg=1>
  1364. <RefPosition #18 @29 RefTypeDef <Ivl:0> LCL_VAR_ADDR BB05 regmask=[rcx] minReg=1>
  1365. <RefPosition #19 @30 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1366. <RefPosition #20 @30 RefTypeUse <Ivl:0> BB05 regmask=[rcx] minReg=1 last fixed>
  1367. <RefPosition #21 @31 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1368. <RefPosition #22 @31 RefTypeDef <Ivl:1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed>
  1369. <RefPosition #23 @32 RefTypeFixedReg <Reg:rcx> BB05 regmask=[rcx] minReg=1>
  1370. <RefPosition #24 @32 RefTypeUse <Ivl:1> BB05 regmask=[rcx] minReg=1 last fixed>
  1371. <RefPosition #25 @33 RefTypeKill <Reg:rax> BB05 regmask=[rax] minReg=1 last>
  1372. <RefPosition #26 @33 RefTypeKill <Reg:rcx> BB05 regmask=[rcx] minReg=1 last>
  1373. <RefPosition #27 @33 RefTypeKill <Reg:rdx> BB05 regmask=[rdx] minReg=1 last>
  1374. <RefPosition #28 @33 RefTypeKill <Reg:r8 > BB05 regmask=[r8] minReg=1 last>
  1375. <RefPosition #29 @33 RefTypeKill <Reg:r9 > BB05 regmask=[r9] minReg=1 last>
  1376. <RefPosition #30 @33 RefTypeKill <Reg:r10> BB05 regmask=[r10] minReg=1 last>
  1377. <RefPosition #31 @33 RefTypeKill <Reg:r11> BB05 regmask=[r11] minReg=1 last>
  1378. <RefPosition #32 @33 RefTypeKill <Reg:mm0> BB05 regmask=[mm0] minReg=1 last>
  1379. <RefPosition #33 @33 RefTypeKill <Reg:mm1> BB05 regmask=[mm1] minReg=1 last>
  1380. <RefPosition #34 @33 RefTypeKill <Reg:mm2> BB05 regmask=[mm2] minReg=1 last>
  1381. <RefPosition #35 @33 RefTypeKill <Reg:mm3> BB05 regmask=[mm3] minReg=1 last>
  1382. <RefPosition #36 @33 RefTypeKill <Reg:mm4> BB05 regmask=[mm4] minReg=1 last>
  1383. <RefPosition #37 @33 RefTypeKill <Reg:mm5> BB05 regmask=[mm5] minReg=1 last>
  1384. Active intervals at end of allocation:
  1385.  
  1386. Trees after linear scan register allocator (LSRA)
  1387.  
  1388. -----------------------------------------------------------------------------------------------------------------------------------------
  1389. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  1390. -----------------------------------------------------------------------------------------------------------------------------------------
  1391. BB01 [0001] 1 1 [???..???) i internal label target LIR
  1392. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  1393. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  1394. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  1395. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  1396. -----------------------------------------------------------------------------------------------------------------------------------------
  1397.  
  1398. ------------ BB01 [???..???), preds={} succs={BB02}
  1399.  
  1400. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  1401. N004 ( 3, 10) [000009] -c---------- t9 = CNS_INT(h) long 0x7fff50fbeaf0 token REG NA
  1402. /--* t9 long
  1403. N006 ( 5, 12) [000010] nc---------- t10 = * IND int REG NA
  1404. N008 ( 1, 1) [000011] -c---------- t11 = CNS_INT int 0 REG NA
  1405. /--* t10 int
  1406. +--* t11 int
  1407. N010 ( 7, 14) [000012] J------N---- * EQ void REG NA
  1408. N012 ( 9, 16) [000018] ------------ * JTRUE void REG NA
  1409.  
  1410. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  1411. N016 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  1412.  
  1413. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  1414.  
  1415. ------------ BB05 [000..008) (return), preds={BB04} succs={}
  1416. N022 (???,???) [000019] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  1417. N024 ( 1, 1) [000000] ------------ NO_OP void REG NA
  1418. N026 (???,???) [000020] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  1419. N028 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1 rcx REG rcx
  1420. /--* t3 long
  1421. N030 (???,???) [000023] ------------ t23 = * PUTARG_REG long REG rcx
  1422. /--* t23 long arg0 in rcx
  1423. N032 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee REG NA
  1424. N034 (???,???) [000021] ------------ IL_OFFSET void IL offset: 0x6 REG NA
  1425. N036 ( 0, 0) [000006] ------------ NOP void REG NA
  1426. N038 (???,???) [000022] ------------ IL_OFFSET void IL offset: 0x7 REG NA
  1427. N040 ( 0, 0) [000008] ------------ RETURN void REG NA
  1428.  
  1429. -------------------------------------------------------------------------------------------------------------------
  1430.  
  1431. Final allocation
  1432. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1433. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1434. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1435. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  1436. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1437. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1438. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1439. 2.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  1440. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1441. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1442. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1443. 14.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  1444. 17.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  1445. 17.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1446. 17.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1447. 17.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1448. 17.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1449. 17.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1450. 17.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1451. 17.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1452. 17.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1453. 17.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1454. 17.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1455. 17.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1456. 17.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1457. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1458. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1459. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1460. 18.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  1461. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1462. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  1463. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  1464. 20.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  1465. 29.#18 I0 Def Alloc rcx | |I0 a| | | | | | | | | | | | |
  1466. 30.#19 rcx Fixd Keep rcx | |I0 a| | | | | | | | | | | | |
  1467. 30.#20 I0 Use * Keep rcx | |I0 i| | | | | | | | | | | | |
  1468. 31.#21 rcx Fixd Keep rcx | | | | | | | | | | | | | | |
  1469. 31.#22 I1 Def Alloc rcx | |I1 a| | | | | | | | | | | | |
  1470. 32.#23 rcx Fixd Keep rcx | |I1 a| | | | | | | | | | | | |
  1471. 32.#24 I1 Use * Keep rcx | |I1 i| | | | | | | | | | | | |
  1472. 33.#25 rax Kill Keep rax | | | | | | | | | | | | | | |
  1473. 33.#26 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  1474. 33.#27 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  1475. 33.#28 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  1476. 33.#29 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  1477. 33.#30 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  1478. 33.#31 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  1479. 33.#32 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  1480. 33.#33 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  1481. 33.#34 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  1482. 33.#35 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  1483. 33.#36 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  1484. 33.#37 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  1485.  
  1486. Recording the maximum number of concurrent spills:
  1487.  
  1488. ----------
  1489. LSRA Stats
  1490. ----------
  1491. Total Tracked Vars: 0
  1492. Total Reg Cand Vars: 0
  1493. Total number of Intervals: 1
  1494. Total number of RefPositions: 37
  1495. Total Spill Count: 0 Weighted: 0
  1496. Total CopyReg Count: 0 Weighted: 0
  1497. Total ResolutionMov Count: 0 Weighted: 0
  1498. Total number of split edges: 0
  1499. Total Number of spill temps created: 0
  1500.  
  1501. TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
  1502. Incoming Parameters:
  1503. BB01 [???..???), preds={} succs={BB02}
  1504. =====
  1505.  
  1506. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  1507. =====
  1508. N004. CNS_INT(h) 0x7fff50fbeaf0 token
  1509. N006. IND
  1510. N008. CNS_INT 0
  1511. N010. EQ
  1512. N012. JTRUE
  1513.  
  1514. BB03 [???..???), preds={BB02} succs={BB04}
  1515. =====
  1516. N016. CALL help
  1517.  
  1518. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  1519. =====
  1520.  
  1521. BB05 [000..008) (return), preds={BB04} succs={}
  1522. =====
  1523. N022. IL_OFFSET IL offset: 0x0
  1524. N024. NO_OP
  1525. N026. IL_OFFSET IL offset: 0x1
  1526. N028. rcx = LCL_VAR_ADDR V01 tmp1 rcx
  1527. N030. rcx = PUTARG_REG; rcx
  1528. N032. CALL ; rcx
  1529. N034. IL_OFFSET IL offset: 0x6
  1530. N036. NOP
  1531. N038. IL_OFFSET IL offset: 0x7
  1532. N040. RETURN
  1533.  
  1534.  
  1535.  
  1536. *************** In genGenerateCode()
  1537.  
  1538. -----------------------------------------------------------------------------------------------------------------------------------------
  1539. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  1540. -----------------------------------------------------------------------------------------------------------------------------------------
  1541. BB01 [0001] 1 1 [???..???) i internal label target LIR
  1542. BB02 [0003] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  1543. BB03 [0004] 1 BB02 0.50 [???..???) internal LIR
  1544. BB04 [0002] 2 BB02,BB03 1 [???..???) i internal label target LIR
  1545. BB05 [0000] 1 BB04 1 [000..008) (return) i gcsafe LIR
  1546. -----------------------------------------------------------------------------------------------------------------------------------------
  1547. *************** In fgDebugCheckBBlist
  1548. Finalizing stack frame
  1549. Modified regs: [rax rcx rdx r8-r11 mm0-mm5]
  1550. Callee-saved registers pushed: 0 []
  1551. *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
  1552. Pad V01 tmp1, size=16, stkOffs=-0x10, pad=0
  1553. Assign V01 tmp1, size=16, stkOffs=-0x20
  1554. Assign V00 OutArgs, size=32, stkOffs=-0x40
  1555. ; Final local variable assignments
  1556. ;
  1557. ; V00 OutArgs [V00 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  1558. ; V01 tmp1 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x10] do-not-enreg[XS] addr-exposed "impSpillStackEnsure"
  1559. ;
  1560. ; Lcl frame size = 48
  1561. Setting stack level from -572662307 to 0
  1562.  
  1563. =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000004.40030060: i internal label target LIR
  1564. BB01 IN (0)={} + ByrefExposed + GcHeap
  1565. OUT(0)={} + ByrefExposed + GcHeap
  1566.  
  1567. Liveness not changing: 0000000000000000 {}
  1568. Live regs: (unchanged) 00000000 {}
  1569. GC regs: (unchanged) 00000000 {}
  1570. Byref regs: (unchanged) 00000000 {}
  1571.  
  1572. L_M17050_BB01:
  1573. Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1574.  
  1575. =============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.40000040: internal LIR
  1576. BB02 IN (0)={} + ByrefExposed + GcHeap
  1577. OUT(0)={} + ByrefExposed + GcHeap
  1578.  
  1579. Liveness not changing: 0000000000000000 {}
  1580. Live regs: (unchanged) 00000000 {}
  1581. GC regs: (unchanged) 00000000 {}
  1582. Byref regs: (unchanged) 00000000 {}
  1583.  
  1584. L_M17050_BB02:
  1585. Added IP mapping: NO_MAP STACK_EMPTY (G_M17050_IG02,ins#0,ofs#0) label
  1586. Generating: N004 ( 3, 10) [000009] -c---------- t9 = CNS_INT(h) long 0x7fff50fbeaf0 token REG NA
  1587. /--* t9 long
  1588. Generating: N006 ( 5, 12) [000010] nc---------- t10 = * IND int REG NA
  1589. Generating: N008 ( 1, 1) [000011] -c---------- t11 = CNS_INT int 0 REG NA
  1590. /--* t10 int
  1591. +--* t11 int
  1592. Generating: N010 ( 7, 14) [000012] J------N---- * EQ void REG NA
  1593. IN0001: cmp dword ptr [(reloc 0x7fff50fbeaf0)], 0
  1594. Generating: N012 ( 9, 16) [000018] ------------ * JTRUE void REG NA
  1595. IN0002: je L_M17050_BB04
  1596.  
  1597. =============== Generating BB03 [???..???), preds={BB02} succs={BB04} flags=0x00000000.40000040: internal LIR
  1598. BB03 IN (0)={} + ByrefExposed + GcHeap
  1599. OUT(0)={} + ByrefExposed + GcHeap
  1600.  
  1601. Liveness not changing: 0000000000000000 {}
  1602. Live regs: (unchanged) 00000000 {}
  1603. GC regs: (unchanged) 00000000 {}
  1604. Byref regs: (unchanged) 00000000 {}
  1605.  
  1606. L_M17050_BB03:
  1607.  
  1608. G_M17050_IG02: ; offs=000000H, funclet=00, bbWeight=1
  1609. Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1610. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  1611. Generating: N016 ( 14, 5) [000013] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  1612. Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1613. IN0003: call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  1614.  
  1615. =============== Generating BB04 [???..???), preds={BB02,BB03} succs={BB05} flags=0x00000000.40030060: i internal label target LIR
  1616. BB04 IN (0)={} + ByrefExposed + GcHeap
  1617. OUT(0)={} + ByrefExposed + GcHeap
  1618.  
  1619. Liveness not changing: 0000000000000000 {}
  1620. Live regs: (unchanged) 00000000 {}
  1621. GC regs: (unchanged) 00000000 {}
  1622. Byref regs: (unchanged) 00000000 {}
  1623.  
  1624. L_M17050_BB04:
  1625.  
  1626. G_M17050_IG03: ; offs=00000DH, funclet=00, bbWeight=0.50
  1627. Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1628. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  1629.  
  1630. =============== Generating BB05 [000..008) (return), preds={BB04} succs={} flags=0x00000004.40080020: i gcsafe LIR
  1631. BB05 IN (0)={} + ByrefExposed + GcHeap
  1632. OUT(0)={} + ByrefExposed + GcHeap
  1633.  
  1634. Liveness not changing: 0000000000000000 {}
  1635. Live regs: (unchanged) 00000000 {}
  1636. GC regs: (unchanged) 00000000 {}
  1637. Byref regs: (unchanged) 00000000 {}
  1638.  
  1639. L_M17050_BB05:
  1640. Added IP mapping: 0x0000 STACK_EMPTY (G_M17050_IG04,ins#0,ofs#0) label
  1641. Generating: N022 (???,???) [000019] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  1642. Generating: N024 ( 1, 1) [000000] ------------ NO_OP void REG NA
  1643. IN0004: nop
  1644. Added IP mapping: 0x0001 STACK_EMPTY (G_M17050_IG04,ins#1,ofs#1)
  1645. Generating: N026 (???,???) [000020] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  1646. Generating: N028 ( 3, 3) [000003] ------------ t3 = LCL_VAR_ADDR long V01 tmp1 rcx REG rcx
  1647. IN0005: lea rcx, [V01 rbp-10H]
  1648. /--* t3 long
  1649. Generating: N030 (???,???) [000023] ------------ t23 = * PUTARG_REG long REG rcx
  1650. /--* t23 long arg0 in rcx
  1651. Generating: N032 ( 17, 9) [000001] S-CXG------- * CALL void CoreLab.Program.Callee REG NA
  1652. Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  1653. Added IP mapping: 0x0001 STACK_EMPTY CALL_INSTRUCTION (G_M17050_IG04,ins#2,ofs#5)
  1654. IN0006: call CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1655. Added IP mapping: 0x0006 (G_M17050_IG04,ins#3,ofs#10)
  1656. Generating: N034 (???,???) [000021] ------------ IL_OFFSET void IL offset: 0x6 REG NA
  1657. Generating: N036 ( 0, 0) [000006] ------------ NOP void REG NA
  1658. IN0007: nop
  1659. Added IP mapping: 0x0007 STACK_EMPTY (G_M17050_IG04,ins#4,ofs#11)
  1660. Generating: N038 (???,???) [000022] ------------ IL_OFFSET void IL offset: 0x7 REG NA
  1661. Generating: N040 ( 0, 0) [000008] ------------ RETURN void REG NA
  1662. IN0008: nop
  1663. Added IP mapping: EPILOG STACK_EMPTY (G_M17050_IG04,ins#5,ofs#12) label
  1664. Reserving epilog IG for block BB05
  1665.  
  1666. G_M17050_IG04: ; offs=000012H, funclet=00, bbWeight=1
  1667. *************** After placeholder IG creation
  1668. G_M17050_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  1669. G_M17050_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1670. G_M17050_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1671. G_M17050_IG04: ; offs=000012H, size=000CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1672. G_M17050_IG05: ; epilog placeholder, next placeholder=<END>, BB05 [0000], epilog, extend <-- First placeholder <-- Last placeholder
  1673. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  1674. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  1675. Liveness not changing: 0000000000000000 {}
  1676.  
  1677. # compCycleEstimate = 41, compSizeEstimate = 31 CoreLab.Program:Caller()
  1678. ; Final local variable assignments
  1679. ;
  1680. ; V00 OutArgs [V00 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  1681. ; V01 tmp1 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x10] do-not-enreg[XS] addr-exposed "impSpillStackEnsure"
  1682. ;
  1683. ; Lcl frame size = 48
  1684. *************** Before prolog / epilog generation
  1685. G_M17050_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  1686. G_M17050_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1687. G_M17050_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1688. G_M17050_IG04: ; offs=000012H, size=000CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1689. G_M17050_IG05: ; epilog placeholder, next placeholder=<END>, BB05 [0000], epilog, extend <-- First placeholder <-- Last placeholder
  1690. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  1691. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  1692. *************** In genFnProlog()
  1693. Added IP mapping to front: PROLOG STACK_EMPTY (G_M17050_IG01,ins#0,ofs#0) label
  1694.  
  1695. __prolog:
  1696. IN0009: push rbp
  1697. IN000a: sub rsp, 48
  1698. IN000b: lea rbp, [rsp+30H]
  1699. *************** In genEnregisterIncomingStackArgs()
  1700.  
  1701.  
  1702. G_M17050_IG01: ; offs=000000H, funclet=00, bbWeight=1
  1703. *************** In genFnEpilog()
  1704.  
  1705. __epilog:
  1706. gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
  1707. IN000c: lea rsp, [rbp]
  1708. IN000d: pop rbp
  1709. IN000e: ret
  1710.  
  1711. G_M17050_IG05: ; offs=00001EH, funclet=00, bbWeight=1
  1712. 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
  1713. *************** After prolog / epilog generation
  1714. G_M17050_IG01: ; func=00, offs=000000H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  1715. G_M17050_IG02: ; offs=00000AH, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1716. G_M17050_IG03: ; offs=000017H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1717. G_M17050_IG04: ; offs=00001CH, size=000CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1718. G_M17050_IG05: ; offs=000028H, size=0006H, epilog, nogc, extend
  1719. *************** In emitJumpDistBind()
  1720. Binding: IN0002: 000000 je L_M17050_BB04
  1721. Binding L_M17050_BB04to G_M17050_IG04
  1722. Estimate of fwd jump [9AC8CFCC/002]: 0011 -> 001C = 0009
  1723. Shrinking jump [9AC8CFCC/002]
  1724. Adjusted offset of BB03 from 0017 to 0013
  1725. Adjusted offset of BB04 from 001C to 0018
  1726. Adjusted offset of BB05 from 0028 to 0024
  1727. Total shrinkage = 4, min extra jump size = 4294967295
  1728.  
  1729. Hot code size = 0x2A bytes
  1730. Cold code size = 0x0 bytes
  1731. reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
  1732. *************** In emitEndCodeGen()
  1733. Converting emitMaxStackDepth from bytes (0) to elements (0)
  1734.  
  1735. ***************************************************************************
  1736. Instructions as they come out of the scheduler
  1737.  
  1738.  
  1739. G_M17050_IG01: ; func=00, offs=000000H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  1740. IN0009: 000000 55 push rbp
  1741. IN000a: 000001 4883EC30 sub rsp, 48
  1742. IN000b: 000005 488D6C2430 lea rbp, [rsp+30H]
  1743. ;; bbWeight=1 PerfScore 1.75
  1744. G_M17050_IG02: ; func=00, offs=00000AH, size=0009H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  1745. IN0001: 00000A 833D9F6D1F0000 cmp dword ptr [(reloc 0x7fff50fbeaf0)], 0
  1746. IN0002: 000011 7405 je SHORT G_M17050_IG04
  1747. ;; bbWeight=1 PerfScore 3.00
  1748. G_M17050_IG03: ; func=00, offs=000013H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1749. [9AC8D6C0] ptr arg pop 0
  1750. IN0003: 000013 E8E8B2A15E call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  1751. ;; bbWeight=0.50 PerfScore 0.50
  1752. G_M17050_IG04: ; func=00, offs=000018H, size=000CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1753. IN0004: 000018 90 nop
  1754. IN0005: 000019 488D4DF0 lea rcx, [rbp-10H]
  1755. [9AC8D6E0] ptr arg pop 0
  1756. IN0006: 00001D E87694FFFF call CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1757. IN0007: 000022 90 nop
  1758. IN0008: 000023 90 nop
  1759. ;; bbWeight=1 PerfScore 2.25
  1760. G_M17050_IG05: ; func=00, offs=000024H, size=0006H, epilog, nogc, extend
  1761. IN000c: 000024 488D6500 lea rsp, [rbp]
  1762. IN000d: 000028 5D pop rbp
  1763. IN000e: 000029 C3 ret
  1764. ;; bbWeight=1 PerfScore 2.00Allocated method code size = 42 , actual size = 42
  1765.  
  1766. ; Total bytes of code 42, prolog size 10, PerfScore 13.70, (MethodHash=4dbcbd65) for method CoreLab.Program:Caller()
  1767. ; ============================================================
  1768.  
  1769. *************** After end code gen, before unwindEmit()
  1770. G_M17050_IG01: ; func=00, offs=000000H, size=000AH, bbWeight=1 PerfScore 1.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  1771.  
  1772. IN0009: 000000 push rbp
  1773. IN000a: 000001 sub rsp, 48
  1774. IN000b: 000005 lea rbp, [rsp+30H]
  1775.  
  1776. G_M17050_IG02: ; offs=00000AH, size=0009H, bbWeight=1 PerfScore 3.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  1777.  
  1778. IN0001: 00000A cmp dword ptr [(reloc 0x7fff50fbeaf0)], 0
  1779. IN0002: 000011 je SHORT G_M17050_IG04
  1780.  
  1781. G_M17050_IG03: ; offs=000013H, size=0005H, bbWeight=0.50 PerfScore 0.50, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1782.  
  1783. IN0003: 000013 call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  1784.  
  1785. G_M17050_IG04: ; offs=000018H, size=000CH, bbWeight=1 PerfScore 2.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  1786.  
  1787. IN0004: 000018 nop
  1788. IN0005: 000019 lea rcx, [V01 rbp-10H]
  1789. IN0006: 00001D call CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1790. IN0007: 000022 nop
  1791. IN0008: 000023 nop
  1792.  
  1793. G_M17050_IG05: ; offs=000024H, size=0006H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend
  1794.  
  1795. IN000c: 000024 lea rsp, [rbp]
  1796. IN000d: 000028 pop rbp
  1797. IN000e: 000029 ret
  1798.  
  1799. Unwind Info:
  1800. >> Start offset : 0x000000 (not in unwind data)
  1801. >> End offset : 0x00002a (not in unwind data)
  1802. Version : 1
  1803. Flags : 0x00
  1804. SizeOfProlog : 0x05
  1805. CountOfUnwindCodes: 2
  1806. FrameRegister : none (0)
  1807. FrameOffset : N/A (no FrameRegister) (Value=0)
  1808. UnwindCodes :
  1809. CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 5 * 8 + 8 = 48 = 0x30
  1810. CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
  1811. allocUnwindInfo(pHotCode=0x00007FFF50DC7D40, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x2a, unwindSize=0x8, pUnwindBlock=0x000002279AC8A778, funKind=0 (main function))
  1812. *************** In genIPmappingGen()
  1813. IP mapping count : 8
  1814. IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
  1815. IL offs NO_MAP : 0x0000000A ( STACK_EMPTY )
  1816. IL offs 0x0000 : 0x00000018 ( STACK_EMPTY )
  1817. IL offs 0x0001 : 0x00000019 ( STACK_EMPTY )
  1818. IL offs 0x0001 : 0x0000001D ( STACK_EMPTY CALL_INSTRUCTION )
  1819. IL offs 0x0006 : 0x00000022
  1820. IL offs 0x0007 : 0x00000023 ( STACK_EMPTY )
  1821. IL offs EPILOG : 0x00000024 ( STACK_EMPTY )
  1822.  
  1823. *************** In genSetScopeInfo()
  1824. VarLocInfo count is 0
  1825. *************** Variable debug info
  1826. 0 live ranges
  1827. *************** In gcInfoBlockHdrSave()
  1828. Set code length to 42.
  1829. Set ReturnKind to Scalar.
  1830. Set stack base register to rbp.
  1831. Set Outgoing stack arg area size to 32.
  1832. Defining interruptible range: [0xa, 0x24).
  1833. Method code size: 42
  1834.  
  1835. Allocations for CoreLab.Program:Caller() (MethodHash=4dbcbd65)
  1836. count: 254, size: 25868, max = 2640
  1837. allocateMemory: 65536, nraUsed: 28280
  1838.  
  1839. Alloc'd bytes by kind:
  1840. kind | size | pct
  1841. ---------------------+------------+--------
  1842. AssertionProp | 0 | 0.00%
  1843. ASTNode | 3328 | 12.87%
  1844. InstDesc | 2880 | 11.13%
  1845. ImpStack | 384 | 1.48%
  1846. BasicBlock | 1936 | 7.48%
  1847. fgArgInfo | 56 | 0.22%
  1848. fgArgInfoPtrArr | 8 | 0.03%
  1849. FlowList | 160 | 0.62%
  1850. TreeStatementList | 0 | 0.00%
  1851. SiScope | 0 | 0.00%
  1852. DominatorMemory | 0 | 0.00%
  1853. LSRA | 3208 | 12.40%
  1854. LSRA_Interval | 176 | 0.68%
  1855. LSRA_RefPosition | 2432 | 9.40%
  1856. Reachability | 0 | 0.00%
  1857. SSA | 0 | 0.00%
  1858. ValueNumber | 0 | 0.00%
  1859. LvaTable | 1920 | 7.42%
  1860. UnwindInfo | 0 | 0.00%
  1861. hashBv | 80 | 0.31%
  1862. bitset | 56 | 0.22%
  1863. FixedBitVect | 8 | 0.03%
  1864. Generic | 1230 | 4.75%
  1865. LocalAddressVisitor | 0 | 0.00%
  1866. FieldSeqStore | 0 | 0.00%
  1867. ZeroOffsetFieldMap | 40 | 0.15%
  1868. ArrayInfoMap | 0 | 0.00%
  1869. MemoryPhiArg | 0 | 0.00%
  1870. CSE | 0 | 0.00%
  1871. GC | 1392 | 5.38%
  1872. CorSig | 104 | 0.40%
  1873. Inlining | 120 | 0.46%
  1874. ArrayStack | 0 | 0.00%
  1875. DebugInfo | 256 | 0.99%
  1876. DebugOnly | 4734 | 18.30%
  1877. Codegen | 1128 | 4.36%
  1878. LoopOpt | 0 | 0.00%
  1879. LoopHoist | 0 | 0.00%
  1880. Unknown | 160 | 0.62%
  1881. RangeCheck | 0 | 0.00%
  1882. CopyProp | 0 | 0.00%
  1883. SideEffects | 0 | 0.00%
  1884. ObjectAllocator | 0 | 0.00%
  1885. VariableLiveRanges | 0 | 0.00%
  1886. ClassLayout | 72 | 0.28%
  1887. TailMergeThrows | 0 | 0.00%
  1888.  
  1889. ****** DONE compiling CoreLab.Program:Caller()
  1890. ****** START compiling CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double] (MethodHash=f5b01313)
  1891. Generating code for Windows x64
  1892. OPTIONS: compCodeOpt = BLENDED_CODE
  1893. OPTIONS: compDbgCode = true
  1894. OPTIONS: compDbgInfo = true
  1895. OPTIONS: compDbgEnC = false
  1896. OPTIONS: compProcedureSplitting = false
  1897. OPTIONS: compProcedureSplittingEH = false
  1898. IL to import:
  1899. IL_0000 00 nop
  1900. IL_0001 12 00 ldloca.s 0x0
  1901. IL_0003 fe 15 01 00 00 1b initobj 0x1B000001
  1902. IL_0009 06 ldloc.0
  1903. IL_000a 0b stloc.1
  1904. IL_000b 2b 00 br.s 0 (IL_000d)
  1905. IL_000d 07 ldloc.1
  1906. IL_000e 2a ret
  1907. HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type Double
  1908. Found type Hardware Intrinsic SIMD Vector128<double>
  1909. Known type Vector128<double>
  1910. '__retBuf' passed in register rcx
  1911. Known type Vector128<double>
  1912. Known type Vector128<double>
  1913.  
  1914. lvaGrabTemp returning 3 (V03 loc2) (a long lifetime temp) called for OutgoingArgSpace.
  1915. ; Initial local variable assignments
  1916. ;
  1917. ; V00 RetBuf byref
  1918. ; V01 loc0 simd16
  1919. ; V02 loc1 simd16
  1920. ; V03 OutArgs lclBlk (na) "OutgoingArgSpace"
  1921. *************** In compInitDebuggingInfo() for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1922. getVars() returned cVars = 0, extendOthers = true
  1923. info.compVarScopesCount = 3
  1924. VarNum LVNum Name Beg End
  1925. 0: 00h 00h V00 RetBuf 000h 00Fh
  1926. 1: 01h 01h V01 loc0 000h 00Fh
  1927. 2: 02h 02h V02 loc1 000h 00Fh
  1928. New Basic Block BB01 [0000] created.
  1929. New scratch BB01
  1930. Debuggable code - Add new BB01 [0000] to perform initialization of variables
  1931. info.compStmtOffsetsCount = 0
  1932. info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE )
  1933. *************** In fgFindBasicBlocks() for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1934. Marked V02 as a single def local
  1935. Jump targets:
  1936. IL_000d
  1937. New Basic Block BB02 [0001] created.
  1938. BB02 [000..00D)
  1939. New Basic Block BB03 [0002] created.
  1940. BB03 [00D..00F)
  1941. CLFLG_MINOPT set for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1942. IL Code Size,Instr 15, 8, Basic Block count 3, Local Variable Num,Ref count 4, 4 for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1943. IL Code Size,Instr 15, 8, Basic Block count 3, Local Variable Num,Ref count 4, 4 for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1944. OPTIONS: opts.MinOpts() == true
  1945. Basic block list for 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  1946.  
  1947. -----------------------------------------------------------------------------------------------------------------------------------------
  1948. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  1949. -----------------------------------------------------------------------------------------------------------------------------------------
  1950. BB01 [0000] 1 1 [???..???) i internal
  1951. BB02 [0001] 1 1 [000..00D)-> BB03 (always)
  1952. BB03 [0002] 1 1 [00D..00F) (return)
  1953. -----------------------------------------------------------------------------------------------------------------------------------------
  1954. *************** In impImport() for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  1955. Marking leading BBF_INTERNAL block BB01 as BBF_IMPORTED
  1956.  
  1957. impImportBlockPending for BB02
  1958.  
  1959. Importing BB02 (PC=000) of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  1960. [ 0] 0 (0x000) nop
  1961.  
  1962. STMT00001 (IL 0x000... ???)
  1963. [000001] ------------ * NO_OP void
  1964.  
  1965. [ 0] 1 (0x001) ldloca.s 0
  1966. [ 1] 3 (0x003) initobj 1B000001
  1967.  
  1968. STMT00002 (IL 0x001... ???)
  1969. [000005] IA---------- * ASG simd16 (init)
  1970. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  1971. [000004] ------------ \--* CNS_INT int 0
  1972.  
  1973. [ 0] 9 (0x009) ldloc.0
  1974. [ 1] 10 (0x00a) stloc.1
  1975.  
  1976. STMT00003 (IL 0x009... ???)
  1977. [000009] -A---------- * ASG simd16 (copy)
  1978. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  1979. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  1980.  
  1981. [ 0] 11 (0x00b) br.s
  1982.  
  1983. STMT00004 (IL 0x00B... ???)
  1984. [000010] ------------ * NOP void
  1985.  
  1986. impImportBlockPending for BB03
  1987.  
  1988. Importing BB03 (PC=013) of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  1989. [ 0] 13 (0x00d) ldloc.1
  1990. [ 1] 14 (0x00e) ret
  1991.  
  1992. STMT00005 (IL 0x00D... ???)
  1993. [000014] -A---------- * ASG simd16 (copy)
  1994. [000013] ------------ +--* IND simd16
  1995. [000012] ------------ | \--* LCL_VAR byref V00 RetBuf
  1996. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  1997.  
  1998.  
  1999. STMT00006 (IL ???... ???)
  2000. [000016] ------------ * RETURN byref
  2001. [000015] ------------ \--* LCL_VAR byref V00 RetBuf
  2002.  
  2003. *************** in fgTransformIndirectCalls(root)
  2004. -- no candidates to transform
  2005.  
  2006. New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
  2007. *************** In fgMorph()
  2008. *************** In fgDebugCheckBBlist
  2009. *************** In Allocate Objects
  2010. Trees before Allocate Objects
  2011.  
  2012. -----------------------------------------------------------------------------------------------------------------------------------------
  2013. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2014. -----------------------------------------------------------------------------------------------------------------------------------------
  2015. BB01 [0000] 1 1 [???..???) i internal
  2016. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  2017. BB03 [0002] 1 1 [00D..00F) (return) i
  2018. -----------------------------------------------------------------------------------------------------------------------------------------
  2019.  
  2020. ------------ BB01 [???..???), preds={} succs={BB02}
  2021.  
  2022. ***** BB01
  2023. STMT00000 (IL ???... ???)
  2024. [000000] ------------ * NOP void
  2025.  
  2026. ------------ BB02 [000..00D) -> BB03 (always), preds={} succs={BB03}
  2027.  
  2028. ***** BB02
  2029. STMT00001 (IL 0x000...0x000)
  2030. [000001] ------------ * NO_OP void
  2031.  
  2032. ***** BB02
  2033. STMT00002 (IL 0x001...0x004)
  2034. [000005] IA---------- * ASG simd16 (init)
  2035. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2036. [000004] ------------ \--* CNS_INT int 0
  2037.  
  2038. ***** BB02
  2039. STMT00003 (IL 0x009...0x00A)
  2040. [000009] -A---------- * ASG simd16 (copy)
  2041. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2042. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2043.  
  2044. ***** BB02
  2045. STMT00004 (IL 0x00B...0x00B)
  2046. [000010] ------------ * NOP void
  2047.  
  2048. ------------ BB03 [00D..00F) (return), preds={} succs={}
  2049.  
  2050. ***** BB03
  2051. STMT00005 (IL 0x00D...0x00E)
  2052. [000014] -A---------- * ASG simd16 (copy)
  2053. [000013] ------------ +--* IND simd16
  2054. [000012] ------------ | \--* LCL_VAR byref V00 RetBuf
  2055. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2056.  
  2057. ***** BB03
  2058. STMT00006 (IL ???... ???)
  2059. [000016] ------------ * RETURN byref
  2060. [000015] ------------ \--* LCL_VAR byref V00 RetBuf
  2061.  
  2062. -------------------------------------------------------------------------------------------------------------------
  2063.  
  2064. *** ObjectAllocationPhase: no newobjs in this method; punting
  2065. *************** Exiting Allocate Objects
  2066. Trees after Allocate Objects
  2067.  
  2068. -----------------------------------------------------------------------------------------------------------------------------------------
  2069. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2070. -----------------------------------------------------------------------------------------------------------------------------------------
  2071. BB01 [0000] 1 1 [???..???) i internal
  2072. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  2073. BB03 [0002] 1 1 [00D..00F) (return) i
  2074. -----------------------------------------------------------------------------------------------------------------------------------------
  2075.  
  2076. ------------ BB01 [???..???), preds={} succs={BB02}
  2077.  
  2078. ***** BB01
  2079. STMT00000 (IL ???... ???)
  2080. [000000] ------------ * NOP void
  2081.  
  2082. ------------ BB02 [000..00D) -> BB03 (always), preds={} succs={BB03}
  2083.  
  2084. ***** BB02
  2085. STMT00001 (IL 0x000...0x000)
  2086. [000001] ------------ * NO_OP void
  2087.  
  2088. ***** BB02
  2089. STMT00002 (IL 0x001...0x004)
  2090. [000005] IA---------- * ASG simd16 (init)
  2091. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2092. [000004] ------------ \--* CNS_INT int 0
  2093.  
  2094. ***** BB02
  2095. STMT00003 (IL 0x009...0x00A)
  2096. [000009] -A---------- * ASG simd16 (copy)
  2097. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2098. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2099.  
  2100. ***** BB02
  2101. STMT00004 (IL 0x00B...0x00B)
  2102. [000010] ------------ * NOP void
  2103.  
  2104. ------------ BB03 [00D..00F) (return), preds={} succs={}
  2105.  
  2106. ***** BB03
  2107. STMT00005 (IL 0x00D...0x00E)
  2108. [000014] -A---------- * ASG simd16 (copy)
  2109. [000013] ------------ +--* IND simd16
  2110. [000012] ------------ | \--* LCL_VAR byref V00 RetBuf
  2111. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2112.  
  2113. ***** BB03
  2114. STMT00006 (IL ???... ???)
  2115. [000016] ------------ * RETURN byref
  2116. [000015] ------------ \--* LCL_VAR byref V00 RetBuf
  2117.  
  2118. -------------------------------------------------------------------------------------------------------------------
  2119.  
  2120. *************** After fgAddInternal()
  2121.  
  2122. -----------------------------------------------------------------------------------------------------------------------------------------
  2123. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2124. -----------------------------------------------------------------------------------------------------------------------------------------
  2125. BB01 [0000] 1 1 [???..???) i internal
  2126. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  2127. BB03 [0002] 1 1 [00D..00F) (return) i
  2128. -----------------------------------------------------------------------------------------------------------------------------------------
  2129.  
  2130. *************** Exception Handling table is empty
  2131. *************** In fgDebugCheckBBlist
  2132.  
  2133. *************** In fgRemoveEmptyTry()
  2134. No EH in this method, nothing to remove.
  2135.  
  2136. *************** In fgRemoveEmptyFinally()
  2137. No EH in this method, nothing to remove.
  2138.  
  2139. *************** In fgMergeFinallyChains()
  2140. No EH in this method, nothing to merge.
  2141.  
  2142. *************** In fgCloneFinally()
  2143. No EH in this method, no cloning.
  2144.  
  2145. *************** In fgResetImplicitByRefRefCount()
  2146. *************** In fgPromoteStructs()
  2147. promotion opt flag not enabled
  2148.  
  2149. *************** In fgMarkAddressExposedLocals()
  2150. LocalAddressVisitor visiting statement:
  2151. STMT00000 (IL ???... ???)
  2152. [000000] ------------ * NOP void
  2153.  
  2154. LocalAddressVisitor visiting statement:
  2155. STMT00007 (IL ???... ???)
  2156. [000024] --C-G------- * QMARK void
  2157. [000020] Q----------- if +--* EQ int
  2158. [000018] ------------ | +--* IND int
  2159. [000017] ------------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  2160. [000019] ------------ | \--* CNS_INT int 0
  2161. [000023] --C-G------- if \--* COLON void
  2162. [000021] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2163. [000022] ------------ then \--* NOP void
  2164.  
  2165. LocalAddressVisitor visiting statement:
  2166. STMT00001 (IL 0x000...0x000)
  2167. [000001] ------------ * NO_OP void
  2168.  
  2169. LocalAddressVisitor visiting statement:
  2170. STMT00002 (IL 0x001...0x004)
  2171. [000005] IA---------- * ASG simd16 (init)
  2172. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2173. [000004] ------------ \--* CNS_INT int 0
  2174.  
  2175. LocalAddressVisitor visiting statement:
  2176. STMT00003 (IL 0x009...0x00A)
  2177. [000009] -A---------- * ASG simd16 (copy)
  2178. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2179. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2180.  
  2181. LocalAddressVisitor visiting statement:
  2182. STMT00004 (IL 0x00B...0x00B)
  2183. [000010] ------------ * NOP void
  2184.  
  2185. LocalAddressVisitor visiting statement:
  2186. STMT00005 (IL 0x00D...0x00E)
  2187. [000014] -A---------- * ASG simd16 (copy)
  2188. [000013] ------------ +--* IND simd16
  2189. [000012] ------------ | \--* LCL_VAR byref V00 RetBuf
  2190. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2191.  
  2192. LocalAddressVisitor visiting statement:
  2193. STMT00006 (IL ???... ???)
  2194. [000016] ------------ * RETURN byref
  2195. [000015] ------------ \--* LCL_VAR byref V00 RetBuf
  2196.  
  2197.  
  2198. *************** In fgRetypeImplicitByRefArgs()
  2199.  
  2200. *************** In fgMorphBlocks()
  2201.  
  2202. Morphing BB01 of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  2203.  
  2204. fgMorphTree BB01, STMT00000 (before)
  2205. [000000] ------------ * NOP void
  2206.  
  2207. fgMorphTree BB01, STMT00007 (before)
  2208. [000024] --C-G------- * QMARK void
  2209. [000020] Q----------- if +--* EQ int
  2210. [000018] ------------ | +--* IND int
  2211. [000017] ------------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  2212. [000019] ------------ | \--* CNS_INT int 0
  2213. [000023] --C-G------- if \--* COLON void
  2214. [000021] --C-G------- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2215. [000022] ------------ then \--* NOP void
  2216. Initializing arg info for 21.CALL:
  2217. ArgTable for 21.CALL after fgInitArgInfo:
  2218.  
  2219. Morphing args for 21.CALL:
  2220. argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32
  2221. ArgTable for 21.CALL after fgMorphArgs:
  2222.  
  2223.  
  2224. Morphing BB02 of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  2225.  
  2226. fgMorphTree BB02, STMT00001 (before)
  2227. [000001] ------------ * NO_OP void
  2228.  
  2229. fgMorphTree BB02, STMT00002 (before)
  2230. [000005] IA---------- * ASG simd16 (init)
  2231. [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2232. [000004] ------------ \--* CNS_INT int 0
  2233.  
  2234. fgMorphInitBlock:fgMorphOneAsgBlock (after):
  2235. [000005] -A---------- * ASG simd16 (copy)
  2236. [000002] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2237. [000025] ------------ \--* SIMD simd16 double init
  2238. [000004] -----+------ \--* CNS_INT int 0
  2239. using oneAsgTree.
  2240.  
  2241. fgMorphTree BB02, STMT00002 (after)
  2242. [000005] -A---+------ * ASG simd16 (copy)
  2243. [000002] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2244. [000025] ------------ \--* SIMD simd16 double init
  2245. [000004] -----+------ \--* CNS_INT int 0
  2246.  
  2247. fgMorphTree BB02, STMT00003 (before)
  2248. [000009] -A---------- * ASG simd16 (copy)
  2249. [000007] D----------- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2250. [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2251.  
  2252. fgMorphCopyBlock:fgMorphOneAsgBlock (after):
  2253. [000009] -A---------- * ASG simd16 (copy)
  2254. [000007] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2255. [000006] -----+------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2256. using oneAsgTree.
  2257.  
  2258. fgMorphCopyBlock (after):
  2259. [000009] -A---------- * ASG simd16 (copy)
  2260. [000007] D----+-N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2261. [000006] -----+------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2262.  
  2263. fgMorphTree BB02, STMT00004 (before)
  2264. [000010] ------------ * NOP void
  2265.  
  2266. Morphing BB03 of 'CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]'
  2267.  
  2268. fgMorphTree BB03, STMT00005 (before)
  2269. [000014] -A---------- * ASG simd16 (copy)
  2270. [000013] ------------ +--* IND simd16
  2271. [000012] ------------ | \--* LCL_VAR byref V00 RetBuf
  2272. [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2273.  
  2274. fgMorphCopyBlock:fgMorphOneAsgBlock (after):
  2275. [000014] -A-XG------- * ASG simd16 (copy)
  2276. [000013] *--XG+-N---- +--* IND simd16
  2277. [000012] -----+------ | \--* LCL_VAR byref V00 RetBuf
  2278. [000011] -----+------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2279. using oneAsgTree.
  2280.  
  2281. fgMorphCopyBlock (after):
  2282. [000014] -A-XG------- * ASG simd16 (copy)
  2283. [000013] *--XG+-N---- +--* IND simd16
  2284. [000012] -----+------ | \--* LCL_VAR byref V00 RetBuf
  2285. [000011] -----+------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2286.  
  2287. fgMorphTree BB03, STMT00006 (before)
  2288. [000016] ------------ * RETURN byref
  2289. [000015] ------------ \--* LCL_VAR byref V00 RetBuf
  2290.  
  2291. Expanding top-level qmark in BB01 (before)
  2292.  
  2293. -----------------------------------------------------------------------------------------------------------------------------------------
  2294. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2295. -----------------------------------------------------------------------------------------------------------------------------------------
  2296. BB01 [0000] 1 1 [???..???) i internal
  2297. -----------------------------------------------------------------------------------------------------------------------------------------
  2298.  
  2299. ------------ BB01 [???..???), preds={} succs={BB02}
  2300.  
  2301. ***** BB01
  2302. STMT00000 (IL ???... ???)
  2303. [000000] -----+------ * NOP void
  2304.  
  2305. ***** BB01
  2306. STMT00007 (IL ???... ???)
  2307. [000024] --C-G+------ * QMARK void
  2308. [000020] J----+-N---- if +--* EQ int
  2309. [000018] n----+------ | +--* IND int
  2310. [000017] -----+------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  2311. [000019] -----+------ | \--* CNS_INT int 0
  2312. [000023] --C-G+?----- if \--* COLON void
  2313. [000021] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2314. [000022] -----+?----- then \--* NOP void
  2315.  
  2316. -------------------------------------------------------------------------------------------------------------------
  2317. New Basic Block BB04 [0003] created.
  2318. BB02 previous predecessor was BB01, now is BB04
  2319. New Basic Block BB05 [0004] created.
  2320. New Basic Block BB06 [0005] created.
  2321.  
  2322. Removing statement STMT00007 (IL ???... ???)
  2323. [000024] --C-G+------ * QMARK void
  2324. [000020] J----+-N---- if +--* EQ int
  2325. [000018] n----+------ | +--* IND int
  2326. [000017] -----+------ | | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  2327. [000019] -----+------ | \--* CNS_INT int 0
  2328. [000023] --C-G+?----- if \--* COLON void
  2329. [000021] --C-G+?----- else +--* CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2330. [000022] -----+?----- then \--* NOP void
  2331. in BB01 as useless:
  2332.  
  2333.  
  2334. Expanding top-level qmark in BB01 (after)
  2335.  
  2336. -----------------------------------------------------------------------------------------------------------------------------------------
  2337. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2338. -----------------------------------------------------------------------------------------------------------------------------------------
  2339. BB01 [0000] 1 1 [???..???) i internal
  2340. BB05 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2341. BB06 [0005] 1 0.50 [???..???) internal
  2342. BB04 [0003] 2 1 [???..???) i internal label target
  2343. -----------------------------------------------------------------------------------------------------------------------------------------
  2344.  
  2345. ------------ BB01 [???..???), preds={} succs={BB05}
  2346.  
  2347. ***** BB01
  2348. STMT00000 (IL ???... ???)
  2349. [000000] -----+------ * NOP void
  2350.  
  2351. ------------ BB05 [???..???) -> BB04 (cond), preds={} succs={BB06,BB04}
  2352.  
  2353. ***** BB05
  2354. STMT00008 (IL ???... ???)
  2355. [000026] ------------ * JTRUE void
  2356. [000020] J----+-N---- \--* EQ int
  2357. [000018] n----+------ +--* IND int
  2358. [000017] -----+------ | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  2359. [000019] -----+------ \--* CNS_INT int 0
  2360.  
  2361. ------------ BB06 [???..???), preds={} succs={BB04}
  2362.  
  2363. ***** BB06
  2364. STMT00009 (IL ???... ???)
  2365. [000021] --C-G+?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2366.  
  2367. ------------ BB04 [???..???), preds={} succs={BB02}
  2368.  
  2369. -------------------------------------------------------------------------------------------------------------------
  2370.  
  2371. Renumbering the basic blocks for fgComputePred
  2372.  
  2373. *************** Before renumbering the basic blocks
  2374.  
  2375. -----------------------------------------------------------------------------------------------------------------------------------------
  2376. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2377. -----------------------------------------------------------------------------------------------------------------------------------------
  2378. BB01 [0000] 1 1 [???..???) i internal
  2379. BB05 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2380. BB06 [0005] 1 0.50 [???..???) internal
  2381. BB04 [0003] 2 1 [???..???) i internal label target
  2382. BB02 [0001] 1 1 [000..00D)-> BB03 (always) i
  2383. BB03 [0002] 1 1 [00D..00F) (return) i
  2384. -----------------------------------------------------------------------------------------------------------------------------------------
  2385.  
  2386. *************** Exception Handling table is empty
  2387. Renumber BB05 to BB02
  2388. Renumber BB06 to BB03
  2389. Renumber BB02 to BB05
  2390. Renumber BB03 to BB06
  2391.  
  2392. *************** After renumbering the basic blocks
  2393.  
  2394. -----------------------------------------------------------------------------------------------------------------------------------------
  2395. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2396. -----------------------------------------------------------------------------------------------------------------------------------------
  2397. BB01 [0000] 1 1 [???..???) i internal
  2398. BB02 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2399. BB03 [0005] 1 0.50 [???..???) internal
  2400. BB04 [0003] 2 1 [???..???) i internal label target
  2401. BB05 [0001] 1 1 [000..00D)-> BB06 (always) i
  2402. BB06 [0002] 1 1 [00D..00F) (return) i
  2403. -----------------------------------------------------------------------------------------------------------------------------------------
  2404.  
  2405. *************** Exception Handling table is empty
  2406.  
  2407. New BlockSet epoch 2, # of blocks (including unused BB00): 7, bitset array size: 1 (short)
  2408.  
  2409. *************** In fgComputePreds()
  2410.  
  2411. -----------------------------------------------------------------------------------------------------------------------------------------
  2412. BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags]
  2413. -----------------------------------------------------------------------------------------------------------------------------------------
  2414. BB01 [0000] 1 1 [???..???) i internal
  2415. BB02 [0004] 1 1 [???..???)-> BB04 ( cond ) internal
  2416. BB03 [0005] 1 0.50 [???..???) internal
  2417. BB04 [0003] 2 1 [???..???) i internal label target
  2418. BB05 [0001] 1 1 [000..00D)-> BB06 (always) i
  2419. BB06 [0002] 1 1 [00D..00F) (return) i
  2420. -----------------------------------------------------------------------------------------------------------------------------------------
  2421.  
  2422.  
  2423. *************** After fgComputePreds()
  2424.  
  2425. -----------------------------------------------------------------------------------------------------------------------------------------
  2426. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2427. -----------------------------------------------------------------------------------------------------------------------------------------
  2428. BB01 [0000] 1 1 [???..???) i internal label target
  2429. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2430. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2431. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2432. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2433. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2434. -----------------------------------------------------------------------------------------------------------------------------------------
  2435.  
  2436. *************** In fgComputeBlockAndEdgeWeights()
  2437.  
  2438. -----------------------------------------------------------------------------------------------------------------------------------------
  2439. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2440. -----------------------------------------------------------------------------------------------------------------------------------------
  2441. BB01 [0000] 1 1 [???..???) i internal label target
  2442. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2443. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2444. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2445. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2446. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2447. -----------------------------------------------------------------------------------------------------------------------------------------
  2448.  
  2449. -- no profile data, so using default called count
  2450. -- not optimizing, so not computing edge weights
  2451. *************** In fgCreateFunclets()
  2452.  
  2453. After fgCreateFunclets()
  2454. -----------------------------------------------------------------------------------------------------------------------------------------
  2455. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2456. -----------------------------------------------------------------------------------------------------------------------------------------
  2457. BB01 [0000] 1 1 [???..???) i internal label target
  2458. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2459. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2460. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2461. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2462. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2463. -----------------------------------------------------------------------------------------------------------------------------------------
  2464.  
  2465. *************** Exception Handling table is empty
  2466. *************** In fgDebugCheckBBlist
  2467.  
  2468. *************** In lvaMarkLocalVars()
  2469. *** lvaComputeRefCounts ***
  2470. *************** In fgFindOperOrder()
  2471. *************** In fgSetBlockOrder()
  2472. The biggest BB has 5 tree nodes
  2473.  
  2474. -----------------------------------------------------------------------------------------------------------------------------------------
  2475. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2476. -----------------------------------------------------------------------------------------------------------------------------------------
  2477. BB01 [0000] 1 1 [???..???) i internal label target
  2478. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2479. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2480. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2481. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2482. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2483. -----------------------------------------------------------------------------------------------------------------------------------------
  2484.  
  2485. ------------ BB01 [???..???), preds={} succs={BB02}
  2486.  
  2487. ***** BB01
  2488. STMT00000 (IL ???... ???)
  2489. N001 ( 0, 0) [000000] ------------ * NOP void
  2490.  
  2491. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2492.  
  2493. ***** BB02
  2494. STMT00008 (IL ???... ???)
  2495. N005 ( 9, 16) [000026] ------------ * JTRUE void
  2496. N004 ( 7, 14) [000020] J------N---- \--* EQ int
  2497. N002 ( 5, 12) [000018] n----------- +--* IND int
  2498. N001 ( 3, 10) [000017] ------------ | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  2499. N003 ( 1, 1) [000019] ------------ \--* CNS_INT int 0
  2500.  
  2501. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2502.  
  2503. ***** BB03
  2504. STMT00009 (IL ???... ???)
  2505. N001 ( 14, 5) [000021] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2506.  
  2507. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2508.  
  2509. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2510.  
  2511. ***** BB05
  2512. STMT00001 (IL 0x000...0x000)
  2513. N001 ( 1, 1) [000001] ------------ * NO_OP void
  2514.  
  2515. ***** BB05
  2516. STMT00002 (IL 0x001...0x004)
  2517. N004 ( 6, 5) [000005] -A------R--- * ASG simd16 (copy)
  2518. N003 ( 3, 2) [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2519. N002 ( 2, 2) [000025] ------------ \--* SIMD simd16 double init
  2520. N001 ( 1, 1) [000004] ------------ \--* CNS_INT int 0
  2521.  
  2522. ***** BB05
  2523. STMT00003 (IL 0x009...0x00A)
  2524. N003 ( 7, 5) [000009] -A------R--- * ASG simd16 (copy)
  2525. N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2526. N001 ( 3, 2) [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2527.  
  2528. ***** BB05
  2529. STMT00004 (IL 0x00B...0x00B)
  2530. N001 ( 0, 0) [000010] ------------ * NOP void
  2531.  
  2532. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2533.  
  2534. ***** BB06
  2535. STMT00005 (IL 0x00D...0x00E)
  2536. N004 ( 10, 7) [000014] -A-XG------- * ASG simd16 (copy)
  2537. N002 ( 6, 4) [000013] *--XG--N---- +--* IND simd16
  2538. N001 ( 3, 2) [000012] ------------ | \--* LCL_VAR byref V00 RetBuf
  2539. N003 ( 3, 2) [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2540.  
  2541. ***** BB06
  2542. STMT00006 (IL ???... ???)
  2543. N002 ( 4, 3) [000016] ------------ * RETURN byref
  2544. N001 ( 3, 2) [000015] ------------ \--* LCL_VAR byref V00 RetBuf
  2545.  
  2546. -------------------------------------------------------------------------------------------------------------------
  2547.  
  2548.  
  2549. *************** In fgDetermineFirstColdBlock()
  2550. No procedure splitting will be done for this method
  2551. *************** In IR Rationalize
  2552. Trees before IR Rationalize
  2553.  
  2554. -----------------------------------------------------------------------------------------------------------------------------------------
  2555. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2556. -----------------------------------------------------------------------------------------------------------------------------------------
  2557. BB01 [0000] 1 1 [???..???) i internal label target
  2558. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal
  2559. BB03 [0005] 1 BB02 0.50 [???..???) internal
  2560. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target
  2561. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i
  2562. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target
  2563. -----------------------------------------------------------------------------------------------------------------------------------------
  2564.  
  2565. ------------ BB01 [???..???), preds={} succs={BB02}
  2566.  
  2567. ***** BB01
  2568. STMT00000 (IL ???... ???)
  2569. N001 ( 0, 0) [000000] ------------ * NOP void
  2570.  
  2571. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2572.  
  2573. ***** BB02
  2574. STMT00008 (IL ???... ???)
  2575. N005 ( 9, 16) [000026] ------------ * JTRUE void
  2576. N004 ( 7, 14) [000020] J------N---- \--* EQ int
  2577. N002 ( 5, 12) [000018] n----------- +--* IND int
  2578. N001 ( 3, 10) [000017] ------------ | \--* CNS_INT(h) long 0x7fff50fbeaf0 token
  2579. N003 ( 1, 1) [000019] ------------ \--* CNS_INT int 0
  2580.  
  2581. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2582.  
  2583. ***** BB03
  2584. STMT00009 (IL ???... ???)
  2585. N001 ( 14, 5) [000021] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2586.  
  2587. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2588.  
  2589. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2590.  
  2591. ***** BB05
  2592. STMT00001 (IL 0x000...0x000)
  2593. N001 ( 1, 1) [000001] ------------ * NO_OP void
  2594.  
  2595. ***** BB05
  2596. STMT00002 (IL 0x001...0x004)
  2597. N004 ( 6, 5) [000005] -A------R--- * ASG simd16 (copy)
  2598. N003 ( 3, 2) [000002] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2599. N002 ( 2, 2) [000025] ------------ \--* SIMD simd16 double init
  2600. N001 ( 1, 1) [000004] ------------ \--* CNS_INT int 0
  2601.  
  2602. ***** BB05
  2603. STMT00003 (IL 0x009...0x00A)
  2604. N003 ( 7, 5) [000009] -A------R--- * ASG simd16 (copy)
  2605. N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2606. N001 ( 3, 2) [000006] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2607.  
  2608. ***** BB05
  2609. STMT00004 (IL 0x00B...0x00B)
  2610. N001 ( 0, 0) [000010] ------------ * NOP void
  2611.  
  2612. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2613.  
  2614. ***** BB06
  2615. STMT00005 (IL 0x00D...0x00E)
  2616. N004 ( 10, 7) [000014] -A-XG------- * ASG simd16 (copy)
  2617. N002 ( 6, 4) [000013] *--XG--N---- +--* IND simd16
  2618. N001 ( 3, 2) [000012] ------------ | \--* LCL_VAR byref V00 RetBuf
  2619. N003 ( 3, 2) [000011] ------------ \--* LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2620.  
  2621. ***** BB06
  2622. STMT00006 (IL ???... ???)
  2623. N002 ( 4, 3) [000016] ------------ * RETURN byref
  2624. N001 ( 3, 2) [000015] ------------ \--* LCL_VAR byref V00 RetBuf
  2625.  
  2626. -------------------------------------------------------------------------------------------------------------------
  2627. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
  2628. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2629.  
  2630. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
  2631. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2632.  
  2633. *************** Exiting IR Rationalize
  2634. Trees after IR Rationalize
  2635.  
  2636. -----------------------------------------------------------------------------------------------------------------------------------------
  2637. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2638. -----------------------------------------------------------------------------------------------------------------------------------------
  2639. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2640. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2641. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2642. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2643. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2644. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2645. -----------------------------------------------------------------------------------------------------------------------------------------
  2646.  
  2647. ------------ BB01 [???..???), preds={} succs={BB02}
  2648. N001 ( 0, 0) [000000] ------------ NOP void
  2649.  
  2650. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2651. N001 ( 3, 10) [000017] ------------ t17 = CNS_INT(h) long 0x7fff50fbeaf0 token
  2652. /--* t17 long
  2653. N002 ( 5, 12) [000018] n----------- t18 = * IND int
  2654. N003 ( 1, 1) [000019] ------------ t19 = CNS_INT int 0
  2655. /--* t18 int
  2656. +--* t19 int
  2657. N004 ( 7, 14) [000020] J------N---- t20 = * EQ int
  2658. /--* t20 int
  2659. N005 ( 9, 16) [000026] ------------ * JTRUE void
  2660.  
  2661. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2662. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2663.  
  2664. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2665.  
  2666. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2667. [000027] ------------ IL_OFFSET void IL offset: 0x0
  2668. N001 ( 1, 1) [000001] ------------ NO_OP void
  2669. [000028] ------------ IL_OFFSET void IL offset: 0x1
  2670. N001 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0
  2671. /--* t4 int
  2672. N002 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init
  2673. /--* t25 simd16
  2674. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2675. [000029] ------------ IL_OFFSET void IL offset: 0x9
  2676. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2677. /--* t6 simd16
  2678. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2679. [000030] ------------ IL_OFFSET void IL offset: 0xb
  2680. N001 ( 0, 0) [000010] ------------ NOP void
  2681.  
  2682. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2683. [000031] ------------ IL_OFFSET void IL offset: 0xd
  2684. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  2685. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2686. /--* t12 byref
  2687. +--* t11 simd16
  2688. [000032] -A-XG------- * STOREIND simd16
  2689. N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf
  2690. /--* t15 byref
  2691. N002 ( 4, 3) [000016] ------------ * RETURN byref
  2692.  
  2693. -------------------------------------------------------------------------------------------------------------------
  2694. *************** In fgDebugCheckBBlist
  2695. Bumping outgoingArgSpaceSize to 32 for call [000021]
  2696. *************** In fgDebugCheckBBlist
  2697. *************** In Lowering
  2698. Trees before Lowering
  2699.  
  2700. -----------------------------------------------------------------------------------------------------------------------------------------
  2701. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2702. -----------------------------------------------------------------------------------------------------------------------------------------
  2703. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2704. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2705. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2706. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2707. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2708. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2709. -----------------------------------------------------------------------------------------------------------------------------------------
  2710.  
  2711. ------------ BB01 [???..???), preds={} succs={BB02}
  2712. N001 ( 0, 0) [000000] ------------ NOP void
  2713.  
  2714. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2715. N001 ( 3, 10) [000017] ------------ t17 = CNS_INT(h) long 0x7fff50fbeaf0 token
  2716. /--* t17 long
  2717. N002 ( 5, 12) [000018] n----------- t18 = * IND int
  2718. N003 ( 1, 1) [000019] ------------ t19 = CNS_INT int 0
  2719. /--* t18 int
  2720. +--* t19 int
  2721. N004 ( 7, 14) [000020] J------N---- t20 = * EQ int
  2722. /--* t20 int
  2723. N005 ( 9, 16) [000026] ------------ * JTRUE void
  2724.  
  2725. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2726. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2727.  
  2728. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2729.  
  2730. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2731. [000027] ------------ IL_OFFSET void IL offset: 0x0
  2732. N001 ( 1, 1) [000001] ------------ NO_OP void
  2733. [000028] ------------ IL_OFFSET void IL offset: 0x1
  2734. N001 ( 1, 1) [000004] ------------ t4 = CNS_INT int 0
  2735. /--* t4 int
  2736. N002 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init
  2737. /--* t25 simd16
  2738. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2739. [000029] ------------ IL_OFFSET void IL offset: 0x9
  2740. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2741. /--* t6 simd16
  2742. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2743. [000030] ------------ IL_OFFSET void IL offset: 0xb
  2744. N001 ( 0, 0) [000010] ------------ NOP void
  2745.  
  2746. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2747. [000031] ------------ IL_OFFSET void IL offset: 0xd
  2748. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  2749. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2750. /--* t12 byref
  2751. +--* t11 simd16
  2752. [000032] -A-XG------- * STOREIND simd16
  2753. N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf
  2754. /--* t15 byref
  2755. N002 ( 4, 3) [000016] ------------ * RETURN byref
  2756.  
  2757. -------------------------------------------------------------------------------------------------------------------
  2758. lowering call (before):
  2759. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2760.  
  2761. objp:
  2762. ======
  2763.  
  2764. args:
  2765. ======
  2766.  
  2767. late:
  2768. ======
  2769. lowering call (after):
  2770. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2771.  
  2772. Lower of StoreInd didn't mark the node as self contained for reason: 4
  2773. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  2774. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2775. /--* t12 byref
  2776. +--* t11 simd16
  2777. [000032] -A-XG------- * STOREIND simd16
  2778. lowering GT_RETURN
  2779. N002 ( 4, 3) [000016] ------------ * RETURN byref
  2780. ============Lower has completed modifying nodes.
  2781.  
  2782. -----------------------------------------------------------------------------------------------------------------------------------------
  2783. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2784. -----------------------------------------------------------------------------------------------------------------------------------------
  2785. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2786. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2787. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2788. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2789. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2790. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2791. -----------------------------------------------------------------------------------------------------------------------------------------
  2792.  
  2793. ------------ BB01 [???..???), preds={} succs={BB02}
  2794. N001 ( 0, 0) [000000] ------------ NOP void
  2795.  
  2796. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2797. N001 ( 3, 10) [000017] -c---------- t17 = CNS_INT(h) long 0x7fff50fbeaf0 token
  2798. /--* t17 long
  2799. N002 ( 5, 12) [000018] nc---------- t18 = * IND int
  2800. N003 ( 1, 1) [000019] -c---------- t19 = CNS_INT int 0
  2801. /--* t18 int
  2802. +--* t19 int
  2803. N004 ( 7, 14) [000020] J------N---- * EQ void
  2804. N005 ( 9, 16) [000026] ------------ * JTRUE void
  2805.  
  2806. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2807. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2808.  
  2809. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2810.  
  2811. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2812. [000027] ------------ IL_OFFSET void IL offset: 0x0
  2813. N001 ( 1, 1) [000001] ------------ NO_OP void
  2814. [000028] ------------ IL_OFFSET void IL offset: 0x1
  2815. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  2816. /--* t4 int
  2817. N002 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init
  2818. /--* t25 simd16
  2819. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2820. [000029] ------------ IL_OFFSET void IL offset: 0x9
  2821. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2822. /--* t6 simd16
  2823. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2824. [000030] ------------ IL_OFFSET void IL offset: 0xb
  2825. N001 ( 0, 0) [000010] ------------ NOP void
  2826.  
  2827. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2828. [000031] ------------ IL_OFFSET void IL offset: 0xd
  2829. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  2830. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2831. /--* t12 byref
  2832. +--* t11 simd16
  2833. [000032] -A-XG------- * STOREIND simd16
  2834. N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf
  2835. /--* t15 byref
  2836. N002 ( 4, 3) [000016] ------------ * RETURN byref
  2837.  
  2838. -------------------------------------------------------------------------------------------------------------------
  2839.  
  2840. *** lvaComputeRefCounts ***
  2841. *************** In fgLocalVarLiveness()
  2842. ; Initial local variable assignments
  2843. ;
  2844. ; V00 RetBuf byref
  2845. ; V01 loc0 simd16 ld-addr-op
  2846. ; V02 loc1 simd16
  2847. ; V03 OutArgs lclBlk (32) "OutgoingArgSpace"
  2848. In fgLocalVarLivenessInit
  2849. *************** In fgPerBlockLocalVarLiveness()
  2850. *************** In fgInterBlockLocalVarLiveness()
  2851. *************** In fgExtendDbgLifetimes()
  2852.  
  2853. Marking vars alive over their entire scope :
  2854.  
  2855. Local variable scopes = 3
  2856. VarNum LVNum Name Beg End
  2857. Sorted by enter scope:
  2858. 0: 01h 01h V01 loc0 000h 00Fh <-- next enter scope
  2859. 1: 02h 02h V02 loc1 000h 00Fh
  2860. 2: 00h 00h V00 RetBuf 000h 00Fh
  2861. Sorted by exit scope:
  2862. 0: 01h 01h V01 loc0 000h 00Fh <-- next exit scope
  2863. 1: 02h 02h V02 loc1 000h 00Fh
  2864. 2: 00h 00h V00 RetBuf 000h 00Fh
  2865. Scope info: block BB01 marking in scope: {}
  2866. Scope info: block BB02 marking in scope: {}
  2867. Scope info: block BB03 marking in scope: {}
  2868. Scope info: block BB04 marking in scope: {}
  2869. Scope info: block BB05 marking in scope: {}
  2870. Scope info: block BB06 marking in scope: {}
  2871.  
  2872. Debug scopes:
  2873. BB01: {}
  2874. BB02: {}
  2875. BB03: {}
  2876. BB04: {}
  2877. BB05: {}
  2878. BB06: {}
  2879. Scope info: block BB01 UNmarking in scope: {}
  2880.  
  2881. BB liveness after fgExtendDbgLifetimes():
  2882.  
  2883. BB01 IN (0)={} + ByrefExposed + GcHeap
  2884. OUT(0)={} + ByrefExposed + GcHeap
  2885.  
  2886. BB02 IN (0)={} + ByrefExposed + GcHeap
  2887. OUT(0)={} + ByrefExposed + GcHeap
  2888.  
  2889. BB03 IN (0)={} + ByrefExposed + GcHeap
  2890. OUT(0)={} + ByrefExposed + GcHeap
  2891.  
  2892. BB04 IN (0)={} + ByrefExposed + GcHeap
  2893. OUT(0)={} + ByrefExposed + GcHeap
  2894.  
  2895. BB05 IN (0)={} + ByrefExposed + GcHeap
  2896. OUT(0)={} + ByrefExposed + GcHeap
  2897.  
  2898. BB06 IN (0)={} + ByrefExposed + GcHeap
  2899. OUT(0)={} + ByrefExposed + GcHeap
  2900.  
  2901.  
  2902.  
  2903. *** lvaComputeRefCounts ***
  2904. Liveness pass finished after lowering, IR:
  2905.  
  2906. -----------------------------------------------------------------------------------------------------------------------------------------
  2907. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2908. -----------------------------------------------------------------------------------------------------------------------------------------
  2909. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2910. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2911. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2912. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2913. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2914. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2915. -----------------------------------------------------------------------------------------------------------------------------------------
  2916.  
  2917. ------------ BB01 [???..???), preds={} succs={BB02}
  2918. N001 ( 0, 0) [000000] ------------ NOP void
  2919.  
  2920. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2921. N001 ( 3, 10) [000017] -c---------- t17 = CNS_INT(h) long 0x7fff50fbeaf0 token
  2922. /--* t17 long
  2923. N002 ( 5, 12) [000018] nc---------- t18 = * IND int
  2924. N003 ( 1, 1) [000019] -c---------- t19 = CNS_INT int 0
  2925. /--* t18 int
  2926. +--* t19 int
  2927. N004 ( 7, 14) [000020] J------N---- * EQ void
  2928. N005 ( 9, 16) [000026] ------------ * JTRUE void
  2929.  
  2930. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2931. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2932.  
  2933. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2934.  
  2935. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2936. [000027] ------------ IL_OFFSET void IL offset: 0x0
  2937. N001 ( 1, 1) [000001] ------------ NO_OP void
  2938. [000028] ------------ IL_OFFSET void IL offset: 0x1
  2939. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  2940. /--* t4 int
  2941. N002 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init
  2942. /--* t25 simd16
  2943. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2944. [000029] ------------ IL_OFFSET void IL offset: 0x9
  2945. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  2946. /--* t6 simd16
  2947. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2948. [000030] ------------ IL_OFFSET void IL offset: 0xb
  2949. N001 ( 0, 0) [000010] ------------ NOP void
  2950.  
  2951. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  2952. [000031] ------------ IL_OFFSET void IL offset: 0xd
  2953. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  2954. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  2955. /--* t12 byref
  2956. +--* t11 simd16
  2957. [000032] -A-XG------- * STOREIND simd16
  2958. N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf
  2959. /--* t15 byref
  2960. N002 ( 4, 3) [000016] ------------ * RETURN byref
  2961.  
  2962. -------------------------------------------------------------------------------------------------------------------
  2963. *************** Exiting Lowering
  2964. Trees after Lowering
  2965.  
  2966. -----------------------------------------------------------------------------------------------------------------------------------------
  2967. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  2968. -----------------------------------------------------------------------------------------------------------------------------------------
  2969. BB01 [0000] 1 1 [???..???) i internal label target LIR
  2970. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  2971. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  2972. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  2973. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  2974. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  2975. -----------------------------------------------------------------------------------------------------------------------------------------
  2976.  
  2977. ------------ BB01 [???..???), preds={} succs={BB02}
  2978. N001 ( 0, 0) [000000] ------------ NOP void
  2979.  
  2980. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  2981. N001 ( 3, 10) [000017] -c---------- t17 = CNS_INT(h) long 0x7fff50fbeaf0 token
  2982. /--* t17 long
  2983. N002 ( 5, 12) [000018] nc---------- t18 = * IND int
  2984. N003 ( 1, 1) [000019] -c---------- t19 = CNS_INT int 0
  2985. /--* t18 int
  2986. +--* t19 int
  2987. N004 ( 7, 14) [000020] J------N---- * EQ void
  2988. N005 ( 9, 16) [000026] ------------ * JTRUE void
  2989.  
  2990. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  2991. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  2992.  
  2993. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  2994.  
  2995. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  2996. [000027] ------------ IL_OFFSET void IL offset: 0x0
  2997. N001 ( 1, 1) [000001] ------------ NO_OP void
  2998. [000028] ------------ IL_OFFSET void IL offset: 0x1
  2999. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  3000. /--* t4 int
  3001. N002 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init
  3002. /--* t25 simd16
  3003. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  3004. [000029] ------------ IL_OFFSET void IL offset: 0x9
  3005. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  3006. /--* t6 simd16
  3007. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  3008. [000030] ------------ IL_OFFSET void IL offset: 0xb
  3009. N001 ( 0, 0) [000010] ------------ NOP void
  3010.  
  3011. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  3012. [000031] ------------ IL_OFFSET void IL offset: 0xd
  3013. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  3014. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  3015. /--* t12 byref
  3016. +--* t11 simd16
  3017. [000032] -A-XG------- * STOREIND simd16
  3018. N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf
  3019. /--* t15 byref
  3020. N002 ( 4, 3) [000016] ------------ * RETURN byref
  3021.  
  3022. -------------------------------------------------------------------------------------------------------------------
  3023. *************** In fgDebugCheckBBlist
  3024. *************** In StackLevelSetter
  3025. Trees before StackLevelSetter
  3026.  
  3027. -----------------------------------------------------------------------------------------------------------------------------------------
  3028. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  3029. -----------------------------------------------------------------------------------------------------------------------------------------
  3030. BB01 [0000] 1 1 [???..???) i internal label target LIR
  3031. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  3032. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  3033. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  3034. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  3035. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  3036. -----------------------------------------------------------------------------------------------------------------------------------------
  3037.  
  3038. ------------ BB01 [???..???), preds={} succs={BB02}
  3039. N001 ( 0, 0) [000000] ------------ NOP void
  3040.  
  3041. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3042. N001 ( 3, 10) [000017] -c---------- t17 = CNS_INT(h) long 0x7fff50fbeaf0 token
  3043. /--* t17 long
  3044. N002 ( 5, 12) [000018] nc---------- t18 = * IND int
  3045. N003 ( 1, 1) [000019] -c---------- t19 = CNS_INT int 0
  3046. /--* t18 int
  3047. +--* t19 int
  3048. N004 ( 7, 14) [000020] J------N---- * EQ void
  3049. N005 ( 9, 16) [000026] ------------ * JTRUE void
  3050.  
  3051. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  3052. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  3053.  
  3054. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3055.  
  3056. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3057. [000027] ------------ IL_OFFSET void IL offset: 0x0
  3058. N001 ( 1, 1) [000001] ------------ NO_OP void
  3059. [000028] ------------ IL_OFFSET void IL offset: 0x1
  3060. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  3061. /--* t4 int
  3062. N002 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init
  3063. /--* t25 simd16
  3064. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  3065. [000029] ------------ IL_OFFSET void IL offset: 0x9
  3066. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  3067. /--* t6 simd16
  3068. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  3069. [000030] ------------ IL_OFFSET void IL offset: 0xb
  3070. N001 ( 0, 0) [000010] ------------ NOP void
  3071.  
  3072. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  3073. [000031] ------------ IL_OFFSET void IL offset: 0xd
  3074. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  3075. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  3076. /--* t12 byref
  3077. +--* t11 simd16
  3078. [000032] -A-XG------- * STOREIND simd16
  3079. N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf
  3080. /--* t15 byref
  3081. N002 ( 4, 3) [000016] ------------ * RETURN byref
  3082.  
  3083. -------------------------------------------------------------------------------------------------------------------
  3084. *************** Exiting StackLevelSetter
  3085. Trees after StackLevelSetter
  3086.  
  3087. -----------------------------------------------------------------------------------------------------------------------------------------
  3088. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  3089. -----------------------------------------------------------------------------------------------------------------------------------------
  3090. BB01 [0000] 1 1 [???..???) i internal label target LIR
  3091. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  3092. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  3093. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  3094. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  3095. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  3096. -----------------------------------------------------------------------------------------------------------------------------------------
  3097.  
  3098. ------------ BB01 [???..???), preds={} succs={BB02}
  3099. N001 ( 0, 0) [000000] ------------ NOP void
  3100.  
  3101. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3102. N001 ( 3, 10) [000017] -c---------- t17 = CNS_INT(h) long 0x7fff50fbeaf0 token
  3103. /--* t17 long
  3104. N002 ( 5, 12) [000018] nc---------- t18 = * IND int
  3105. N003 ( 1, 1) [000019] -c---------- t19 = CNS_INT int 0
  3106. /--* t18 int
  3107. +--* t19 int
  3108. N004 ( 7, 14) [000020] J------N---- * EQ void
  3109. N005 ( 9, 16) [000026] ------------ * JTRUE void
  3110.  
  3111. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  3112. N001 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE
  3113.  
  3114. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3115.  
  3116. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3117. [000027] ------------ IL_OFFSET void IL offset: 0x0
  3118. N001 ( 1, 1) [000001] ------------ NO_OP void
  3119. [000028] ------------ IL_OFFSET void IL offset: 0x1
  3120. N001 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0
  3121. /--* t4 int
  3122. N002 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init
  3123. /--* t25 simd16
  3124. N004 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  3125. [000029] ------------ IL_OFFSET void IL offset: 0x9
  3126. N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0
  3127. /--* t6 simd16
  3128. N003 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  3129. [000030] ------------ IL_OFFSET void IL offset: 0xb
  3130. N001 ( 0, 0) [000010] ------------ NOP void
  3131.  
  3132. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  3133. [000031] ------------ IL_OFFSET void IL offset: 0xd
  3134. N001 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf
  3135. N003 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1
  3136. /--* t12 byref
  3137. +--* t11 simd16
  3138. [000032] -A-XG------- * STOREIND simd16
  3139. N001 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf
  3140. /--* t15 byref
  3141. N002 ( 4, 3) [000016] ------------ * RETURN byref
  3142.  
  3143. -------------------------------------------------------------------------------------------------------------------
  3144. *************** In fgDebugCheckBBlist
  3145. Clearing modified regs.
  3146.  
  3147. buildIntervals ========
  3148.  
  3149. -----------------
  3150. LIVENESS:
  3151. -----------------
  3152. BB01 use def in out
  3153. {}
  3154. {}
  3155. {}
  3156. {}
  3157. BB02 use def in out
  3158. {}
  3159. {}
  3160. {}
  3161. {}
  3162. BB03 use def in out
  3163. {}
  3164. {}
  3165. {}
  3166. {}
  3167. BB04 use def in out
  3168. {}
  3169. {}
  3170. {}
  3171. {}
  3172. BB05 use def in out
  3173. {}
  3174. {}
  3175. {}
  3176. {}
  3177. BB06 use def in out
  3178. {}
  3179. {}
  3180. {}
  3181. {}
  3182.  
  3183. FP callee save candidate vars: None
  3184.  
  3185. floatVarCount = 0; hasLoops = 0, singleExit = 1
  3186. TUPLE STYLE DUMP BEFORE LSRA
  3187. LSRA Block Sequence: BB01( 1 )
  3188. BB02( 1 )
  3189. BB03( 0.50)
  3190. BB04( 1 )
  3191. BB05( 1 )
  3192. BB06( 1 )
  3193.  
  3194. BB01 [???..???), preds={} succs={BB02}
  3195. =====
  3196. N001. NOP
  3197.  
  3198. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3199. =====
  3200. N001. CNS_INT(h) 0x7fff50fbeaf0 token
  3201. N002. IND
  3202. N003. CNS_INT 0
  3203. N004. EQ
  3204. N005. JTRUE
  3205.  
  3206. BB03 [???..???), preds={BB02} succs={BB04}
  3207. =====
  3208. N001. CALL help
  3209.  
  3210. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3211. =====
  3212.  
  3213. BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3214. =====
  3215. N000. IL_OFFSET IL offset: 0x0
  3216. N001. NO_OP
  3217. N000. IL_OFFSET IL offset: 0x1
  3218. N001. CNS_INT 0
  3219. N002. t25 = SIMD
  3220. N004. V01 MEM; t25
  3221. N000. IL_OFFSET IL offset: 0x9
  3222. N001. t6 = V01 MEM
  3223. N003. V02 MEM; t6
  3224. N000. IL_OFFSET IL offset: 0xb
  3225. N001. NOP
  3226.  
  3227. BB06 [00D..00F) (return), preds={BB05} succs={}
  3228. =====
  3229. N000. IL_OFFSET IL offset: 0xd
  3230. N001. t12 = V00 MEM
  3231. N003. t11 = V02 MEM
  3232. N000. STOREIND ; t12,t11
  3233. N001. t15 = V00 MEM
  3234. N002. RETURN ; t15
  3235.  
  3236.  
  3237.  
  3238.  
  3239. buildIntervals second part ========
  3240. Int arg V00 in reg rcx
  3241.  
  3242. NEW BLOCK BB01
  3243. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3244.  
  3245. DefList: { }
  3246. N002 ( 0, 0) [000000] ------------ * NOP void REG NA
  3247.  
  3248.  
  3249. NEW BLOCK BB02
  3250.  
  3251.  
  3252. Setting BB01 as the predecessor for determining incoming variable registers of BB02
  3253. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3254.  
  3255. DefList: { }
  3256. N006 ( 3, 10) [000017] -c---------- * CNS_INT(h) long 0x7fff50fbeaf0 token REG NA
  3257. Contained
  3258. DefList: { }
  3259. N008 ( 5, 12) [000018] nc---------- * IND int REG NA
  3260. Contained
  3261. DefList: { }
  3262. N010 ( 1, 1) [000019] -c---------- * CNS_INT int 0 REG NA
  3263. Contained
  3264. DefList: { }
  3265. N012 ( 7, 14) [000020] J------N---- * EQ void REG NA
  3266.  
  3267. DefList: { }
  3268. N014 ( 9, 16) [000026] ------------ * JTRUE void REG NA
  3269.  
  3270.  
  3271. NEW BLOCK BB03
  3272.  
  3273.  
  3274. Setting BB02 as the predecessor for determining incoming variable registers of BB03
  3275. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3276.  
  3277. DefList: { }
  3278. N018 ( 14, 5) [000021] --C-G-?----- * CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  3279. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1>
  3280. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1>
  3281. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1>
  3282. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1>
  3283. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1>
  3284. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1>
  3285. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1>
  3286. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1>
  3287. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1>
  3288. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1>
  3289. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1>
  3290. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1>
  3291. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1>
  3292.  
  3293.  
  3294. NEW BLOCK BB04
  3295.  
  3296.  
  3297. Setting BB02 as the predecessor for determining incoming variable registers of BB04
  3298. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3299.  
  3300.  
  3301. NEW BLOCK BB05
  3302.  
  3303.  
  3304. Setting BB04 as the predecessor for determining incoming variable registers of BB05
  3305. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3306.  
  3307. DefList: { }
  3308. N024 (???,???) [000027] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
  3309.  
  3310. DefList: { }
  3311. N026 ( 1, 1) [000001] ------------ * NO_OP void REG NA
  3312.  
  3313. DefList: { }
  3314. N028 (???,???) [000028] ------------ * IL_OFFSET void IL offset: 0x1 REG NA
  3315.  
  3316. DefList: { }
  3317. N030 ( 1, 1) [000004] -c---------- * CNS_INT int 0 REG NA
  3318. Contained
  3319. DefList: { }
  3320. N032 ( 2, 2) [000025] ------------ * SIMD simd16 double init REG NA
  3321. Interval 0: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  3322. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[allFloat] minReg=1>
  3323.  
  3324. DefList: { N032.t25. SIMD }
  3325. N034 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0 NA REG NA
  3326. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  3327.  
  3328. DefList: { }
  3329. N036 (???,???) [000029] ------------ * IL_OFFSET void IL offset: 0x9 REG NA
  3330.  
  3331. DefList: { }
  3332. N038 ( 3, 2) [000006] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0 NA REG NA
  3333. Interval 1: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  3334. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[allFloat] minReg=1>
  3335.  
  3336. DefList: { N038.t6. LCL_VAR }
  3337. N040 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1 NA REG NA
  3338. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[allFloat] minReg=1 last>
  3339.  
  3340. DefList: { }
  3341. N042 (???,???) [000030] ------------ * IL_OFFSET void IL offset: 0xb REG NA
  3342.  
  3343. DefList: { }
  3344. N044 ( 0, 0) [000010] ------------ * NOP void REG NA
  3345.  
  3346.  
  3347. NEW BLOCK BB06
  3348.  
  3349.  
  3350. Setting BB05 as the predecessor for determining incoming variable registers of BB06
  3351. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3352.  
  3353. DefList: { }
  3354. N048 (???,???) [000031] ------------ * IL_OFFSET void IL offset: 0xd REG NA
  3355.  
  3356. DefList: { }
  3357. N050 ( 3, 2) [000012] ------------ * LCL_VAR byref V00 RetBuf NA REG NA
  3358. Interval 2: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
  3359. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
  3360.  
  3361. DefList: { N050.t12. LCL_VAR }
  3362. N052 ( 3, 2) [000011] ------------ * LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1 NA REG NA
  3363. Interval 3: simd16 RefPositions {} physReg:NA Preferences=[allFloat]
  3364. <RefPosition #24 @53 RefTypeDef <Ivl:3> LCL_VAR BB06 regmask=[allFloat] minReg=1>
  3365.  
  3366. DefList: { N050.t12. LCL_VAR; N052.t11. LCL_VAR }
  3367. N054 (???,???) [000032] -A-XG------- * STOREIND simd16 REG NA
  3368. <RefPosition #25 @54 RefTypeUse <Ivl:2> BB06 regmask=[allIntButFP] minReg=1 last>
  3369. <RefPosition #26 @54 RefTypeUse <Ivl:3> BB06 regmask=[allFloat] minReg=1 last>
  3370.  
  3371. DefList: { }
  3372. N056 ( 3, 2) [000015] ------------ * LCL_VAR byref V00 RetBuf NA REG NA
  3373. Interval 4: byref RefPositions {} physReg:NA Preferences=[allIntButFP]
  3374. <RefPosition #27 @57 RefTypeDef <Ivl:4> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
  3375.  
  3376. DefList: { N056.t15. LCL_VAR }
  3377. N058 ( 4, 3) [000016] ------------ * RETURN byref REG NA
  3378. <RefPosition #28 @58 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
  3379. <RefPosition #29 @58 RefTypeUse <Ivl:4> BB06 regmask=[rax] minReg=1 last fixed>
  3380.  
  3381.  
  3382. Linear scan intervals BEFORE VALIDATING INTERVALS:
  3383. Interval 0: simd16 RefPositions {#18@33 #19@34} physReg:NA Preferences=[allFloat]
  3384. Interval 1: simd16 RefPositions {#20@39 #21@40} physReg:NA Preferences=[allFloat]
  3385. Interval 2: byref RefPositions {#23@51 #25@54} physReg:NA Preferences=[allIntButFP]
  3386. Interval 3: simd16 RefPositions {#24@53 #26@54} physReg:NA Preferences=[allFloat]
  3387. Interval 4: byref RefPositions {#27@57 #29@58} physReg:NA Preferences=[rax]
  3388.  
  3389. ------------
  3390. REFPOSITIONS BEFORE VALIDATING INTERVALS:
  3391. ------------
  3392. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3393. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3394. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3395. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  3396. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  3397. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  3398. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  3399. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  3400. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  3401. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  3402. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  3403. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  3404. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  3405. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  3406. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  3407. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  3408. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3409. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3410. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[allFloat] minReg=1>
  3411. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  3412. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[allFloat] minReg=1>
  3413. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[allFloat] minReg=1 last>
  3414. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3415. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
  3416. <RefPosition #24 @53 RefTypeDef <Ivl:3> LCL_VAR BB06 regmask=[allFloat] minReg=1>
  3417. <RefPosition #25 @54 RefTypeUse <Ivl:2> BB06 regmask=[allIntButFP] minReg=1 last>
  3418. <RefPosition #26 @54 RefTypeUse <Ivl:3> BB06 regmask=[allFloat] minReg=1 last>
  3419. <RefPosition #27 @57 RefTypeDef <Ivl:4> LCL_VAR BB06 regmask=[rax] minReg=1>
  3420. <RefPosition #28 @58 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
  3421. <RefPosition #29 @58 RefTypeUse <Ivl:4> BB06 regmask=[rax] minReg=1 last fixed>
  3422. TUPLE STYLE DUMP WITH REF POSITIONS
  3423. Incoming Parameters:
  3424. BB01 [???..???), preds={} succs={BB02}
  3425. =====
  3426. N002. NOP
  3427.  
  3428. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3429. =====
  3430. N006. CNS_INT(h) 0x7fff50fbeaf0 token
  3431. N008. IND
  3432. N010. CNS_INT 0
  3433. N012. EQ
  3434. N014. JTRUE
  3435.  
  3436. BB03 [???..???), preds={BB02} succs={BB04}
  3437. =====
  3438. N018. CALL help
  3439. Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5
  3440.  
  3441. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3442. =====
  3443.  
  3444. BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3445. =====
  3446. N024. IL_OFFSET IL offset: 0x0
  3447. N026. NO_OP
  3448. N028. IL_OFFSET IL offset: 0x1
  3449. N030. CNS_INT 0
  3450. N032. SIMD
  3451. Def:<I0>(#18)
  3452. N034. V01 MEM
  3453. Use:<I0>(#19) *
  3454. N036. IL_OFFSET IL offset: 0x9
  3455. N038. V01 MEM
  3456. Def:<I1>(#20)
  3457. N040. V02 MEM
  3458. Use:<I1>(#21) *
  3459. N042. IL_OFFSET IL offset: 0xb
  3460. N044. NOP
  3461.  
  3462. BB06 [00D..00F) (return), preds={BB05} succs={}
  3463. =====
  3464. N048. IL_OFFSET IL offset: 0xd
  3465. N050. V00 MEM
  3466. Def:<I2>(#23)
  3467. N052. V02 MEM
  3468. Def:<I3>(#24)
  3469. N054. STOREIND
  3470. Use:<I2>(#25) *
  3471. Use:<I3>(#26) *
  3472. N056. V00 MEM
  3473. Def:<I4>(#27)
  3474. N058. RETURN
  3475. Use:<I4>(#29) Fixed:rax(#28) *
  3476.  
  3477.  
  3478.  
  3479.  
  3480. Linear scan intervals after buildIntervals:
  3481. Interval 0: simd16 RefPositions {#18@33 #19@34} physReg:NA Preferences=[allFloat]
  3482. Interval 1: simd16 RefPositions {#20@39 #21@40} physReg:NA Preferences=[allFloat]
  3483. Interval 2: byref RefPositions {#23@51 #25@54} physReg:NA Preferences=[allIntButFP]
  3484. Interval 3: simd16 RefPositions {#24@53 #26@54} physReg:NA Preferences=[allFloat]
  3485. Interval 4: byref RefPositions {#27@57 #29@58} physReg:NA Preferences=[rax]
  3486.  
  3487. *************** In LinearScan::allocateRegisters()
  3488.  
  3489. Linear scan intervals before allocateRegisters:
  3490. Interval 0: simd16 RefPositions {#18@33 #19@34} physReg:NA Preferences=[allFloat]
  3491. Interval 1: simd16 RefPositions {#20@39 #21@40} physReg:NA Preferences=[allFloat]
  3492. Interval 2: byref RefPositions {#23@51 #25@54} physReg:NA Preferences=[allIntButFP]
  3493. Interval 3: simd16 RefPositions {#24@53 #26@54} physReg:NA Preferences=[allFloat]
  3494. Interval 4: byref RefPositions {#27@57 #29@58} physReg:NA Preferences=[rax]
  3495.  
  3496. ------------
  3497. REFPOSITIONS BEFORE ALLOCATION:
  3498. ------------
  3499. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3500. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3501. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3502. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  3503. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  3504. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  3505. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  3506. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  3507. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  3508. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  3509. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  3510. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  3511. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  3512. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  3513. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  3514. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  3515. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3516. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3517. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[allFloat] minReg=1>
  3518. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[allFloat] minReg=1 last>
  3519. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[allFloat] minReg=1>
  3520. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[allFloat] minReg=1 last>
  3521. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3522. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[allIntButFP] minReg=1>
  3523. <RefPosition #24 @53 RefTypeDef <Ivl:3> LCL_VAR BB06 regmask=[allFloat] minReg=1>
  3524. <RefPosition #25 @54 RefTypeUse <Ivl:2> BB06 regmask=[allIntButFP] minReg=1 last>
  3525. <RefPosition #26 @54 RefTypeUse <Ivl:3> BB06 regmask=[allFloat] minReg=1 last>
  3526. <RefPosition #27 @57 RefTypeDef <Ivl:4> LCL_VAR BB06 regmask=[rax] minReg=1>
  3527. <RefPosition #28 @58 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
  3528. <RefPosition #29 @58 RefTypeUse <Ivl:4> BB06 regmask=[rax] minReg=1 last fixed>
  3529.  
  3530.  
  3531. Allocating Registers
  3532. --------------------
  3533. The following table has one or more rows for each RefPosition that is handled during allocation.
  3534. The first column provides the basic information about the RefPosition, with its type (e.g. Def,
  3535. Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
  3536. action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
  3537. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
  3538. active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive.
  3539. Columns are only printed up to the last modifed register, which may increase during allocation,
  3540. in which case additional columns will appear.
  3541. Registers which are not marked modified have ---- in their column.
  3542.  
  3543. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3544. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3545. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3546. | | | | | | | | | | | | | | |
  3547. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  3548. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3549. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3550. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3551. 4.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  3552. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3553. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3554. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3555. 16.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  3556. 19.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  3557. 19.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  3558. 19.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  3559. 19.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  3560. 19.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  3561. 19.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  3562. 19.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  3563. 19.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  3564. 19.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  3565. 19.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  3566. 19.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  3567. 19.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  3568. 19.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  3569. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3570. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3571. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3572. 20.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  3573. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3574. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3575. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3576. 22.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  3577. 33.#18 I0 Def Alloc mm0 | | | | | | | | | |I0 a| | | | |
  3578. 34.#19 I0 Use * Keep mm0 | | | | | | | | | |I0 a| | | | |
  3579. 39.#20 I1 Def Alloc mm0 | | | | | | | | | |I1 a| | | | |
  3580. 40.#21 I1 Use * Keep mm0 | | | | | | | | | |I1 a| | | | |
  3581. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3582. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3583. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3584. 46.#22 BB6 PredBB5 | | | | | | | | | | | | | | |
  3585. 51.#23 I2 Def Alloc rax |I2 a| | | | | | | | | | | | | |
  3586. 53.#24 I3 Def Alloc mm0 |I2 a| | | | | | | | |I3 a| | | | |
  3587. 54.#25 I2 Use * Keep rax |I2 a| | | | | | | | |I3 a| | | | |
  3588. 54.#26 I3 Use * Keep mm0 |I2 a| | | | | | | | |I3 a| | | | |
  3589. 57.#27 I4 Def Alloc rax |I4 a| | | | | | | | | | | | | |
  3590. 58.#28 rax Fixd Keep rax |I4 a| | | | | | | | | | | | | |
  3591. 58.#29 I4 Use * Keep rax | | | | | | | | | | | | | | |
  3592.  
  3593. ------------
  3594. REFPOSITIONS AFTER ALLOCATION:
  3595. ------------
  3596. <RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
  3597. <RefPosition #1 @4 RefTypeBB BB02 regmask=[] minReg=1>
  3598. <RefPosition #2 @16 RefTypeBB BB03 regmask=[] minReg=1>
  3599. <RefPosition #3 @19 RefTypeKill <Reg:rax> BB03 regmask=[rax] minReg=1 last>
  3600. <RefPosition #4 @19 RefTypeKill <Reg:rcx> BB03 regmask=[rcx] minReg=1 last>
  3601. <RefPosition #5 @19 RefTypeKill <Reg:rdx> BB03 regmask=[rdx] minReg=1 last>
  3602. <RefPosition #6 @19 RefTypeKill <Reg:r8 > BB03 regmask=[r8] minReg=1 last>
  3603. <RefPosition #7 @19 RefTypeKill <Reg:r9 > BB03 regmask=[r9] minReg=1 last>
  3604. <RefPosition #8 @19 RefTypeKill <Reg:r10> BB03 regmask=[r10] minReg=1 last>
  3605. <RefPosition #9 @19 RefTypeKill <Reg:r11> BB03 regmask=[r11] minReg=1 last>
  3606. <RefPosition #10 @19 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
  3607. <RefPosition #11 @19 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
  3608. <RefPosition #12 @19 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
  3609. <RefPosition #13 @19 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
  3610. <RefPosition #14 @19 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
  3611. <RefPosition #15 @19 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
  3612. <RefPosition #16 @20 RefTypeBB BB04 regmask=[] minReg=1>
  3613. <RefPosition #17 @22 RefTypeBB BB05 regmask=[] minReg=1>
  3614. <RefPosition #18 @33 RefTypeDef <Ivl:0> SIMD BB05 regmask=[mm0] minReg=1>
  3615. <RefPosition #19 @34 RefTypeUse <Ivl:0> BB05 regmask=[mm0] minReg=1 last>
  3616. <RefPosition #20 @39 RefTypeDef <Ivl:1> LCL_VAR BB05 regmask=[mm0] minReg=1>
  3617. <RefPosition #21 @40 RefTypeUse <Ivl:1> BB05 regmask=[mm0] minReg=1 last>
  3618. <RefPosition #22 @46 RefTypeBB BB06 regmask=[] minReg=1>
  3619. <RefPosition #23 @51 RefTypeDef <Ivl:2> LCL_VAR BB06 regmask=[rax] minReg=1>
  3620. <RefPosition #24 @53 RefTypeDef <Ivl:3> LCL_VAR BB06 regmask=[mm0] minReg=1>
  3621. <RefPosition #25 @54 RefTypeUse <Ivl:2> BB06 regmask=[rax] minReg=1 last>
  3622. <RefPosition #26 @54 RefTypeUse <Ivl:3> BB06 regmask=[mm0] minReg=1 last>
  3623. <RefPosition #27 @57 RefTypeDef <Ivl:4> LCL_VAR BB06 regmask=[rax] minReg=1>
  3624. <RefPosition #28 @58 RefTypeFixedReg <Reg:rax> BB06 regmask=[rax] minReg=1>
  3625. <RefPosition #29 @58 RefTypeUse <Ivl:4> BB06 regmask=[rax] minReg=1 last fixed>
  3626. Active intervals at end of allocation:
  3627.  
  3628. Trees after linear scan register allocator (LSRA)
  3629.  
  3630. -----------------------------------------------------------------------------------------------------------------------------------------
  3631. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  3632. -----------------------------------------------------------------------------------------------------------------------------------------
  3633. BB01 [0000] 1 1 [???..???) i internal label target LIR
  3634. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  3635. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  3636. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  3637. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  3638. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  3639. -----------------------------------------------------------------------------------------------------------------------------------------
  3640.  
  3641. ------------ BB01 [???..???), preds={} succs={BB02}
  3642. N002 ( 0, 0) [000000] ------------ NOP void REG NA
  3643.  
  3644. ------------ BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3645. N006 ( 3, 10) [000017] -c---------- t17 = CNS_INT(h) long 0x7fff50fbeaf0 token REG NA
  3646. /--* t17 long
  3647. N008 ( 5, 12) [000018] nc---------- t18 = * IND int REG NA
  3648. N010 ( 1, 1) [000019] -c---------- t19 = CNS_INT int 0 REG NA
  3649. /--* t18 int
  3650. +--* t19 int
  3651. N012 ( 7, 14) [000020] J------N---- * EQ void REG NA
  3652. N014 ( 9, 16) [000026] ------------ * JTRUE void REG NA
  3653.  
  3654. ------------ BB03 [???..???), preds={BB02} succs={BB04}
  3655. N018 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  3656.  
  3657. ------------ BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3658.  
  3659. ------------ BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3660. N024 (???,???) [000027] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  3661. N026 ( 1, 1) [000001] ------------ NO_OP void REG NA
  3662. N028 (???,???) [000028] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  3663. N030 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA
  3664. /--* t4 int
  3665. N032 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init REG mm0
  3666. /--* t25 simd16
  3667. N034 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0 NA REG NA
  3668. N036 (???,???) [000029] ------------ IL_OFFSET void IL offset: 0x9 REG NA
  3669. N038 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0 mm0 REG mm0
  3670. /--* t6 simd16
  3671. N040 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1 NA REG NA
  3672. N042 (???,???) [000030] ------------ IL_OFFSET void IL offset: 0xb REG NA
  3673. N044 ( 0, 0) [000010] ------------ NOP void REG NA
  3674.  
  3675. ------------ BB06 [00D..00F) (return), preds={BB05} succs={}
  3676. N048 (???,???) [000031] ------------ IL_OFFSET void IL offset: 0xd REG NA
  3677. N050 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf rax REG rax
  3678. N052 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1 mm0 REG mm0
  3679. /--* t12 byref
  3680. +--* t11 simd16
  3681. N054 (???,???) [000032] -A-XG------- * STOREIND simd16 REG NA
  3682. N056 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf rax REG rax
  3683. /--* t15 byref
  3684. N058 ( 4, 3) [000016] ------------ * RETURN byref REG NA
  3685.  
  3686. -------------------------------------------------------------------------------------------------------------------
  3687.  
  3688. Final allocation
  3689. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3690. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3691. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3692. 0.#0 BB1 PredBB0 | | | | | | | | | | | | | | |
  3693. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3694. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3695. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3696. 4.#1 BB2 PredBB1 | | | | | | | | | | | | | | |
  3697. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3698. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3699. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3700. 16.#2 BB3 PredBB2 | | | | | | | | | | | | | | |
  3701. 19.#3 rax Kill Keep rax | | | | | | | | | | | | | | |
  3702. 19.#4 rcx Kill Keep rcx | | | | | | | | | | | | | | |
  3703. 19.#5 rdx Kill Keep rdx | | | | | | | | | | | | | | |
  3704. 19.#6 r8 Kill Keep r8 | | | | | | | | | | | | | | |
  3705. 19.#7 r9 Kill Keep r9 | | | | | | | | | | | | | | |
  3706. 19.#8 r10 Kill Keep r10 | | | | | | | | | | | | | | |
  3707. 19.#9 r11 Kill Keep r11 | | | | | | | | | | | | | | |
  3708. 19.#10 mm0 Kill Keep mm0 | | | | | | | | | | | | | | |
  3709. 19.#11 mm1 Kill Keep mm1 | | | | | | | | | | | | | | |
  3710. 19.#12 mm2 Kill Keep mm2 | | | | | | | | | | | | | | |
  3711. 19.#13 mm3 Kill Keep mm3 | | | | | | | | | | | | | | |
  3712. 19.#14 mm4 Kill Keep mm4 | | | | | | | | | | | | | | |
  3713. 19.#15 mm5 Kill Keep mm5 | | | | | | | | | | | | | | |
  3714. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3715. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3716. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3717. 20.#16 BB4 PredBB2 | | | | | | | | | | | | | | |
  3718. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3719. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3720. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3721. 22.#17 BB5 PredBB4 | | | | | | | | | | | | | | |
  3722. 33.#18 I0 Def Alloc mm0 | | | | | | | | | |I0 a| | | | |
  3723. 34.#19 I0 Use * Keep mm0 | | | | | | | | | |I0 i| | | | |
  3724. 39.#20 I1 Def Alloc mm0 | | | | | | | | | |I1 a| | | | |
  3725. 40.#21 I1 Use * Keep mm0 | | | | | | | | | |I1 i| | | | |
  3726. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3727. LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |
  3728. ------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
  3729. 46.#22 BB6 PredBB5 | | | | | | | | | | | | | | |
  3730. 51.#23 I2 Def Alloc rax |I2 a| | | | | | | | | | | | | |
  3731. 53.#24 I3 Def Alloc mm0 |I2 a| | | | | | | | |I3 a| | | | |
  3732. 54.#25 I2 Use * Keep rax |I2 i| | | | | | | | |I3 a| | | | |
  3733. 54.#26 I3 Use * Keep mm0 | | | | | | | | | |I3 i| | | | |
  3734. 57.#27 I4 Def Alloc rax |I4 a| | | | | | | | | | | | | |
  3735. 58.#28 rax Fixd Keep rax |I4 a| | | | | | | | | | | | | |
  3736. 58.#29 I4 Use * Keep rax |I4 i| | | | | | | | | | | | | |
  3737.  
  3738. Recording the maximum number of concurrent spills:
  3739.  
  3740. ----------
  3741. LSRA Stats
  3742. ----------
  3743. Total Tracked Vars: 0
  3744. Total Reg Cand Vars: 0
  3745. Total number of Intervals: 4
  3746. Total number of RefPositions: 29
  3747. Total Spill Count: 0 Weighted: 0
  3748. Total CopyReg Count: 0 Weighted: 0
  3749. Total ResolutionMov Count: 0 Weighted: 0
  3750. Total number of split edges: 0
  3751. Total Number of spill temps created: 0
  3752.  
  3753. TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
  3754. Incoming Parameters:
  3755. BB01 [???..???), preds={} succs={BB02}
  3756. =====
  3757. N002. NOP
  3758.  
  3759. BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04}
  3760. =====
  3761. N006. CNS_INT(h) 0x7fff50fbeaf0 token
  3762. N008. IND
  3763. N010. CNS_INT 0
  3764. N012. EQ
  3765. N014. JTRUE
  3766.  
  3767. BB03 [???..???), preds={BB02} succs={BB04}
  3768. =====
  3769. N018. CALL help
  3770.  
  3771. BB04 [???..???), preds={BB02,BB03} succs={BB05}
  3772. =====
  3773.  
  3774. BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06}
  3775. =====
  3776. N024. IL_OFFSET IL offset: 0x0
  3777. N026. NO_OP
  3778. N028. IL_OFFSET IL offset: 0x1
  3779. N030. CNS_INT 0
  3780. N032. mm0 = SIMD
  3781. N034. V01 MEM; mm0
  3782. N036. IL_OFFSET IL offset: 0x9
  3783. N038. mm0 = V01 MEM
  3784. N040. V02 MEM; mm0
  3785. N042. IL_OFFSET IL offset: 0xb
  3786. N044. NOP
  3787.  
  3788. BB06 [00D..00F) (return), preds={BB05} succs={}
  3789. =====
  3790. N048. IL_OFFSET IL offset: 0xd
  3791. N050. rax = V00 MEM
  3792. N052. mm0 = V02 MEM
  3793. N054. STOREIND ; rax,mm0
  3794. N056. rax = V00 MEM
  3795. N058. RETURN ; rax
  3796.  
  3797.  
  3798.  
  3799. *************** In genGenerateCode()
  3800.  
  3801. -----------------------------------------------------------------------------------------------------------------------------------------
  3802. BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags]
  3803. -----------------------------------------------------------------------------------------------------------------------------------------
  3804. BB01 [0000] 1 1 [???..???) i internal label target LIR
  3805. BB02 [0004] 1 BB01 1 [???..???)-> BB04 ( cond ) internal LIR
  3806. BB03 [0005] 1 BB02 0.50 [???..???) internal LIR
  3807. BB04 [0003] 2 BB02,BB03 1 [???..???) i internal label target LIR
  3808. BB05 [0001] 1 BB04 1 [000..00D)-> BB06 (always) i LIR
  3809. BB06 [0002] 1 BB05 1 [00D..00F) (return) i label target LIR
  3810. -----------------------------------------------------------------------------------------------------------------------------------------
  3811. *************** In fgDebugCheckBBlist
  3812. Finalizing stack frame
  3813. Modified regs: [rax rcx rdx r8-r11 mm0-mm5]
  3814. Callee-saved registers pushed: 0 []
  3815. *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
  3816. Pad V01 loc0, size=16, stkOffs=-0x10, pad=0
  3817. Assign V01 loc0, size=16, stkOffs=-0x20
  3818. Pad V02 loc1, size=16, stkOffs=-0x20, pad=0
  3819. Assign V02 loc1, size=16, stkOffs=-0x30
  3820. Assign V03 OutArgs, size=32, stkOffs=-0x50
  3821. ; Final local variable assignments
  3822. ;
  3823. ; V00 RetBuf [V00 ] ( 1, 1 ) byref -> [rbp+0x10]
  3824. ; V01 loc0 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x10] must-init ld-addr-op
  3825. ; V02 loc1 [V02 ] ( 1, 1 ) simd16 -> [rbp-0x20] must-init
  3826. ; V03 OutArgs [V03 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  3827. ;
  3828. ; Lcl frame size = 64
  3829. Setting stack level from -572662307 to 0
  3830.  
  3831. =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000004.40030060: i internal label target LIR
  3832. BB01 IN (0)={} + ByrefExposed + GcHeap
  3833. OUT(0)={} + ByrefExposed + GcHeap
  3834.  
  3835. Liveness not changing: 0000000000000000 {}
  3836. Live regs: (unchanged) 00000000 {}
  3837. GC regs: (unchanged) 00000000 {}
  3838. Byref regs: (unchanged) 00000000 {}
  3839.  
  3840. L_M60652_BB01:
  3841. Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3842.  
  3843. Scope info: begin block BB01, IL range [???..???)
  3844. Scope info: ignoring block beginning
  3845. Generating: N002 ( 0, 0) [000000] ------------ NOP void REG NA
  3846.  
  3847. Scope info: end block BB01, IL range [???..???)
  3848. Scope info: ignoring block end
  3849.  
  3850. =============== Generating BB02 [???..???) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.40000040: internal LIR
  3851. BB02 IN (0)={} + ByrefExposed + GcHeap
  3852. OUT(0)={} + ByrefExposed + GcHeap
  3853.  
  3854. Liveness not changing: 0000000000000000 {}
  3855. Live regs: (unchanged) 00000000 {}
  3856. GC regs: (unchanged) 00000000 {}
  3857. Byref regs: (unchanged) 00000000 {}
  3858.  
  3859. L_M60652_BB02:
  3860.  
  3861. Scope info: begin block BB02, IL range [???..???)
  3862. Scope info: ignoring block beginning
  3863. Added IP mapping: NO_MAP STACK_EMPTY (G_M60652_IG02,ins#0,ofs#0) label
  3864. Generating: N006 ( 3, 10) [000017] -c---------- t17 = CNS_INT(h) long 0x7fff50fbeaf0 token REG NA
  3865. /--* t17 long
  3866. Generating: N008 ( 5, 12) [000018] nc---------- t18 = * IND int REG NA
  3867. Generating: N010 ( 1, 1) [000019] -c---------- t19 = CNS_INT int 0 REG NA
  3868. /--* t18 int
  3869. +--* t19 int
  3870. Generating: N012 ( 7, 14) [000020] J------N---- * EQ void REG NA
  3871. IN0001: cmp dword ptr [(reloc 0x7fff50fbeaf0)], 0
  3872. Generating: N014 ( 9, 16) [000026] ------------ * JTRUE void REG NA
  3873. IN0002: je L_M60652_BB04
  3874.  
  3875. Scope info: end block BB02, IL range [???..???)
  3876. Scope info: ignoring block end
  3877.  
  3878. =============== Generating BB03 [???..???), preds={BB02} succs={BB04} flags=0x00000000.40000040: internal LIR
  3879. BB03 IN (0)={} + ByrefExposed + GcHeap
  3880. OUT(0)={} + ByrefExposed + GcHeap
  3881.  
  3882. Liveness not changing: 0000000000000000 {}
  3883. Live regs: (unchanged) 00000000 {}
  3884. GC regs: (unchanged) 00000000 {}
  3885. Byref regs: (unchanged) 00000000 {}
  3886.  
  3887. L_M60652_BB03:
  3888.  
  3889. G_M60652_IG02: ; offs=000000H, funclet=00, bbWeight=1
  3890. Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3891.  
  3892. Scope info: begin block BB03, IL range [???..???)
  3893. Scope info: ignoring block beginning
  3894. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  3895. Generating: N018 ( 14, 5) [000021] --C-G-?----- CALL help void HELPER.CORINFO_HELP_DBG_IS_JUST_MY_CODE REG NA
  3896. Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3897. IN0003: call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  3898.  
  3899. Scope info: end block BB03, IL range [???..???)
  3900. Scope info: ignoring block end
  3901.  
  3902. =============== Generating BB04 [???..???), preds={BB02,BB03} succs={BB05} flags=0x00000000.40030060: i internal label target LIR
  3903. BB04 IN (0)={} + ByrefExposed + GcHeap
  3904. OUT(0)={} + ByrefExposed + GcHeap
  3905.  
  3906. Liveness not changing: 0000000000000000 {}
  3907. Live regs: (unchanged) 00000000 {}
  3908. GC regs: (unchanged) 00000000 {}
  3909. Byref regs: (unchanged) 00000000 {}
  3910.  
  3911. L_M60652_BB04:
  3912.  
  3913. G_M60652_IG03: ; offs=00000DH, funclet=00, bbWeight=0.50
  3914. Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3915.  
  3916. Scope info: begin block BB04, IL range [???..???)
  3917. Scope info: ignoring block beginning
  3918. genIPmappingAdd: ignoring duplicate IL offset 0xffffffff
  3919.  
  3920. Scope info: end block BB04, IL range [???..???)
  3921. Scope info: ignoring block end
  3922.  
  3923. =============== Generating BB05 [000..00D) -> BB06 (always), preds={BB04} succs={BB06} flags=0x00000000.40000020: i LIR
  3924. BB05 IN (0)={} + ByrefExposed + GcHeap
  3925. OUT(0)={} + ByrefExposed + GcHeap
  3926.  
  3927. Liveness not changing: 0000000000000000 {}
  3928. Live regs: (unchanged) 00000000 {}
  3929. GC regs: (unchanged) 00000000 {}
  3930. Byref regs: (unchanged) 00000000 {}
  3931.  
  3932. L_M60652_BB05:
  3933.  
  3934. Scope info: begin block BB05, IL range [000..00D)
  3935. Scope info: opening scope, LVnum=1 [000..00F)
  3936. Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
  3937. Scope info: opening scope, LVnum=2 [000..00F)
  3938. Scope info: >> new scope, VarNum=2, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
  3939. Scope info: opening scope, LVnum=0 [000..00F)
  3940. Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=0000000000000000 {}
  3941. Scope info: open scopes =
  3942. 1 (V01 loc0) [000..00F)
  3943. 2 (V02 loc1) [000..00F)
  3944. 0 (V00 RetBuf) [000..00F)
  3945. Added IP mapping: 0x0000 STACK_EMPTY (G_M60652_IG04,ins#0,ofs#0) label
  3946. Generating: N024 (???,???) [000027] ------------ IL_OFFSET void IL offset: 0x0 REG NA
  3947. Generating: N026 ( 1, 1) [000001] ------------ NO_OP void REG NA
  3948. IN0004: nop
  3949. Added IP mapping: 0x0001 STACK_EMPTY (G_M60652_IG04,ins#1,ofs#1)
  3950. Generating: N028 (???,???) [000028] ------------ IL_OFFSET void IL offset: 0x1 REG NA
  3951. Generating: N030 ( 1, 1) [000004] -c---------- t4 = CNS_INT int 0 REG NA
  3952. /--* t4 int
  3953. Generating: N032 ( 2, 2) [000025] ------------ t25 = * SIMD simd16 double init REG mm0
  3954. IN0005: vxorps xmm0, xmm0
  3955. /--* t25 simd16
  3956. Generating: N034 ( 6, 5) [000005] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0 NA REG NA
  3957. IN0006: vmovapd xmmword ptr [V01 rbp-10H], xmm0
  3958. Added IP mapping: 0x0009 STACK_EMPTY (G_M60652_IG04,ins#3,ofs#12)
  3959. Generating: N036 (???,???) [000029] ------------ IL_OFFSET void IL offset: 0x9 REG NA
  3960. Generating: N038 ( 3, 2) [000006] ------------ t6 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V01 loc0 mm0 REG mm0
  3961. IN0007: vmovapd xmm0, xmmword ptr [V01 rbp-10H]
  3962. /--* t6 simd16
  3963. Generating: N040 ( 7, 5) [000009] DA---------- * STORE_LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1 NA REG NA
  3964. IN0008: vmovapd xmmword ptr [V02 rbp-20H], xmm0
  3965. Added IP mapping: 0x000B STACK_EMPTY (G_M60652_IG04,ins#5,ofs#24)
  3966. Generating: N042 (???,???) [000030] ------------ IL_OFFSET void IL offset: 0xb REG NA
  3967. Generating: N044 ( 0, 0) [000010] ------------ NOP void REG NA
  3968. IN0009: nop
  3969.  
  3970. Scope info: end block BB05, IL range [000..00D)
  3971. Scope info: open scopes =
  3972. 1 (V01 loc0) [000..00F)
  3973. 2 (V02 loc1) [000..00F)
  3974. 0 (V00 RetBuf) [000..00F)
  3975. IN000a: jmp L_M60652_BB06
  3976.  
  3977. =============== Generating BB06 [00D..00F) (return), preds={BB05} succs={} flags=0x00000000.40030020: i label target LIR
  3978. BB06 IN (0)={} + ByrefExposed + GcHeap
  3979. OUT(0)={} + ByrefExposed + GcHeap
  3980.  
  3981. Liveness not changing: 0000000000000000 {}
  3982. Live regs: (unchanged) 00000000 {}
  3983. GC regs: (unchanged) 00000000 {}
  3984. Byref regs: (unchanged) 00000000 {}
  3985.  
  3986. L_M60652_BB06:
  3987.  
  3988. G_M60652_IG04: ; offs=000012H, funclet=00, bbWeight=1
  3989. Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
  3990.  
  3991. Scope info: begin block BB06, IL range [00D..00F)
  3992. Scope info: open scopes =
  3993. 1 (V01 loc0) [000..00F)
  3994. 2 (V02 loc1) [000..00F)
  3995. 0 (V00 RetBuf) [000..00F)
  3996. Added IP mapping: 0x000D STACK_EMPTY (G_M60652_IG05,ins#0,ofs#0) label
  3997. Generating: N048 (???,???) [000031] ------------ IL_OFFSET void IL offset: 0xd REG NA
  3998. Generating: N050 ( 3, 2) [000012] ------------ t12 = LCL_VAR byref V00 RetBuf rax REG rax
  3999. IN000b: mov rax, bword ptr [V00 rbp+10H]
  4000. Byref regs: 00000000 {} => 00000001 {rax}
  4001. Generating: N052 ( 3, 2) [000011] ------------ t11 = LCL_VAR simd16<System.Runtime.Intrinsics.Vector128`1[Double]> V02 loc1 mm0 REG mm0
  4002. IN000c: vmovapd xmm0, xmmword ptr [V02 rbp-20H]
  4003. /--* t12 byref
  4004. +--* t11 simd16
  4005. Generating: N054 (???,???) [000032] -A-XG------- * STOREIND simd16 REG NA
  4006. Byref regs: 00000001 {rax} => 00000000 {}
  4007. IN000d: vmovupd xmmword ptr [rax], xmm0
  4008. Generating: N056 ( 3, 2) [000015] ------------ t15 = LCL_VAR byref V00 RetBuf rax REG rax
  4009. IN000e: mov rax, bword ptr [V00 rbp+10H]
  4010. Byref regs: 00000000 {} => 00000001 {rax}
  4011. /--* t15 byref
  4012. Generating: N058 ( 4, 3) [000016] ------------ * RETURN byref REG NA
  4013. Byref regs: 00000001 {rax} => 00000000 {}
  4014.  
  4015. Scope info: end block BB06, IL range [00D..00F)
  4016. Scope info: ending scope, LVnum=1 [000..00F)
  4017. Scope info: ending scope, LVnum=2 [000..00F)
  4018. Scope info: ending scope, LVnum=0 [000..00F)
  4019. Scope info: open scopes =
  4020. <none>
  4021. Added IP mapping: EPILOG STACK_EMPTY (G_M60652_IG05,ins#4,ofs#19) label
  4022. Reserving epilog IG for block BB06
  4023.  
  4024. G_M60652_IG05: ; offs=000030H, funclet=00, bbWeight=1
  4025. *************** After placeholder IG creation
  4026. G_M60652_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  4027. G_M60652_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4028. G_M60652_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4029. G_M60652_IG04: ; offs=000012H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4030. G_M60652_IG05: ; offs=000030H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4031. G_M60652_IG06: ; epilog placeholder, next placeholder=<END>, BB06 [0002], epilog, extend <-- First placeholder <-- Last placeholder
  4032. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  4033. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  4034. Liveness not changing: 0000000000000000 {}
  4035.  
  4036. # compCycleEstimate = 51, compSizeEstimate = 42 CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  4037. ; Final local variable assignments
  4038. ;
  4039. ; V00 RetBuf [V00 ] ( 1, 1 ) byref -> [rbp+0x10]
  4040. ; V01 loc0 [V01 ] ( 1, 1 ) simd16 -> [rbp-0x10] must-init ld-addr-op
  4041. ; V02 loc1 [V02 ] ( 1, 1 ) simd16 -> [rbp-0x20] must-init
  4042. ; V03 OutArgs [V03 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace"
  4043. ;
  4044. ; Lcl frame size = 64
  4045. *************** Before prolog / epilog generation
  4046. G_M60652_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
  4047. G_M60652_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4048. G_M60652_IG03: ; offs=00000DH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4049. G_M60652_IG04: ; offs=000012H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4050. G_M60652_IG05: ; offs=000030H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4051. G_M60652_IG06: ; epilog placeholder, next placeholder=<END>, BB06 [0002], epilog, extend <-- First placeholder <-- Last placeholder
  4052. ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
  4053. ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
  4054. *************** In genFnProlog()
  4055. Added IP mapping to front: PROLOG STACK_EMPTY (G_M60652_IG01,ins#0,ofs#0) label
  4056.  
  4057. __prolog:
  4058. Found 8 lvMustInit int-sized stack slots, frame offsets 32 through 0
  4059. IN000f: push rbp
  4060. IN0010: sub rsp, 64
  4061. IN0011: vzeroupper
  4062. IN0012: lea rbp, [rsp+40H]
  4063. IN0013: xor rax, rax
  4064. IN0014: mov qword ptr [V01 rbp-10H], rax
  4065. IN0015: mov qword ptr [V01+0x8 rbp-08H], rax
  4066. IN0016: mov qword ptr [V02 rbp-20H], rax
  4067. IN0017: mov qword ptr [V02+0x8 rbp-18H], rax
  4068. *************** In genFnPrologCalleeRegArgs() for int regs
  4069. IN0018: mov bword ptr [V00 rbp+10H], rcx
  4070. *************** In genEnregisterIncomingStackArgs()
  4071.  
  4072.  
  4073. G_M60652_IG01: ; offs=000000H, funclet=00, bbWeight=1
  4074. *************** In genFnEpilog()
  4075.  
  4076. __epilog:
  4077. gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
  4078. IN0019: lea rsp, [rbp]
  4079. IN001a: pop rbp
  4080. IN001b: ret
  4081.  
  4082. G_M60652_IG06: ; offs=000043H, funclet=00, bbWeight=1
  4083. 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
  4084. *************** After prolog / epilog generation
  4085. G_M60652_IG01: ; func=00, offs=000000H, size=0023H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  4086. G_M60652_IG02: ; offs=000023H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4087. G_M60652_IG03: ; offs=000030H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4088. G_M60652_IG04: ; offs=000035H, size=001EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4089. G_M60652_IG05: ; offs=000053H, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4090. G_M60652_IG06: ; offs=000066H, size=0006H, epilog, nogc, extend
  4091. *************** In emitJumpDistBind()
  4092. Binding: IN0002: 000000 je L_M60652_BB04
  4093. Binding L_M60652_BB04to G_M60652_IG04
  4094. Estimate of fwd jump [9AC8DB84/002]: 002A -> 0035 = 0009
  4095. Shrinking jump [9AC8DB84/002]
  4096. Adjusted offset of BB03 from 0030 to 002C
  4097. Adjusted offset of BB04 from 0035 to 0031
  4098. Binding: IN000a: 000000 jmp L_M60652_BB06
  4099. Binding L_M60652_BB06to G_M60652_IG05
  4100. Estimate of fwd jump [9AC8E094/010]: 004A -> 004F = 0003
  4101. Shrinking jump [9AC8E094/010]
  4102. Adjusted offset of BB05 from 0053 to 004C
  4103. Adjusted offset of BB06 from 0066 to 005F
  4104. Total shrinkage = 7, min extra jump size = 4294967295
  4105.  
  4106. Hot code size = 0x65 bytes
  4107. Cold code size = 0x0 bytes
  4108. reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
  4109. *************** In emitEndCodeGen()
  4110. Converting emitMaxStackDepth from bytes (0) to elements (0)
  4111.  
  4112. ***************************************************************************
  4113. Instructions as they come out of the scheduler
  4114.  
  4115.  
  4116. G_M60652_IG01: ; func=00, offs=000000H, size=0023H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  4117. IN000f: 000000 55 push rbp
  4118. IN0010: 000001 4883EC40 sub rsp, 64
  4119. IN0011: 000005 C5F877 vzeroupper
  4120. IN0012: 000008 488D6C2440 lea rbp, [rsp+40H]
  4121. IN0013: 00000D 33C0 xor rax, rax
  4122. IN0014: 00000F 488945F0 mov qword ptr [rbp-10H], rax
  4123. IN0015: 000013 488945F8 mov qword ptr [rbp-08H], rax
  4124. IN0016: 000017 488945E0 mov qword ptr [rbp-20H], rax
  4125. IN0017: 00001B 488945E8 mov qword ptr [rbp-18H], rax
  4126. IN0018: 00001F 48894D10 mov bword ptr [rbp+10H], rcx
  4127. ;; bbWeight=1 PerfScore 8.00
  4128. G_M60652_IG02: ; func=00, offs=000023H, size=0009H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  4129. IN0001: 000023 833D466D1F0000 cmp dword ptr [(reloc 0x7fff50fbeaf0)], 0
  4130. IN0002: 00002A 7405 je SHORT G_M60652_IG04
  4131. ;; bbWeight=1 PerfScore 3.00
  4132. G_M60652_IG03: ; func=00, offs=00002CH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4133. [9AC8E7A0] ptr arg pop 0
  4134. IN0003: 00002C E88FB2A15E call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  4135. ;; bbWeight=0.50 PerfScore 0.50
  4136. G_M60652_IG04: ; func=00, offs=000031H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  4137. IN0004: 000031 90 nop
  4138. IN0005: 000032 C5F857C0 vxorps xmm0, xmm0 (ECS:5, ACS:4)
  4139. Instruction predicted size = 5, actual = 4
  4140. IN0006: 000036 C5F92945F0 vmovapd xmmword ptr [rbp-10H], xmm0 (ECS:6, ACS:5)
  4141. Instruction predicted size = 6, actual = 5
  4142. IN0007: 00003B C5F92845F0 vmovapd xmm0, xmmword ptr [rbp-10H] (ECS:6, ACS:5)
  4143. Instruction predicted size = 6, actual = 5
  4144. IN0008: 000040 C5F92945E0 vmovapd xmmword ptr [rbp-20H], xmm0 (ECS:6, ACS:5)
  4145. Instruction predicted size = 6, actual = 5
  4146. IN0009: 000045 90 nop
  4147. IN000a: 000046 EB04 jmp SHORT G_M60652_IG05
  4148. ;; bbWeight=1 PerfScore 9.83
  4149. G_M60652_IG05: ; func=00, offs=00004CH, size=0013H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4150. Block predicted offs = 0000004C, actual = 00000048 -> size adj = 4
  4151. byrReg +[rax]
  4152. IN000b: 000048 488B4510 mov rax, bword ptr [rbp+10H]
  4153. IN000c: 00004C C5F92845E0 vmovapd xmm0, xmmword ptr [rbp-20H] (ECS:6, ACS:5)
  4154. Instruction predicted size = 6, actual = 5
  4155. IN000d: 000051 C5F91100 vmovupd xmmword ptr [rax], xmm0 (ECS:5, ACS:4)
  4156. Instruction predicted size = 5, actual = 4
  4157. IN000e: 000055 488B4510 mov rax, bword ptr [rbp+10H]
  4158. ;; bbWeight=1 PerfScore 8.00
  4159. G_M60652_IG06: ; func=00, offs=00005FH, size=0006H, epilog, nogc, extend
  4160. Block predicted offs = 0000005F, actual = 00000059 -> size adj = 6
  4161. IN0019: 000059 488D6500 lea rsp, [rbp]
  4162. IN001a: 00005D 5D pop rbp
  4163. IN001b: 00005E C3 ret
  4164. ;; bbWeight=1 PerfScore 2.00New byrReg live regs=00000000 {}
  4165. byrReg -[rax]
  4166. Allocated method code size = 101 , actual size = 95
  4167.  
  4168. ; Total bytes of code 95, prolog size 35, PerfScore 41.43, (MethodHash=f5b01313) for method CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
  4169. ; ============================================================
  4170.  
  4171. *************** After end code gen, before unwindEmit()
  4172. G_M60652_IG01: ; func=00, offs=000000H, size=0023H, bbWeight=1 PerfScore 8.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
  4173.  
  4174. IN000f: 000000 push rbp
  4175. IN0010: 000001 sub rsp, 64
  4176. IN0011: 000005 vzeroupper
  4177. IN0012: 000008 lea rbp, [rsp+40H]
  4178. IN0013: 00000D xor rax, rax
  4179. IN0014: 00000F mov qword ptr [V01 rbp-10H], rax
  4180. IN0015: 000013 mov qword ptr [V01+0x8 rbp-08H], rax
  4181. IN0016: 000017 mov qword ptr [V02 rbp-20H], rax
  4182. IN0017: 00001B mov qword ptr [V02+0x8 rbp-18H], rax
  4183. IN0018: 00001F mov bword ptr [V00 rbp+10H], rcx
  4184.  
  4185. G_M60652_IG02: ; offs=000023H, size=0009H, bbWeight=1 PerfScore 3.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  4186.  
  4187. IN0001: 000023 cmp dword ptr [(reloc 0x7fff50fbeaf0)], 0
  4188. IN0002: 00002A je SHORT G_M60652_IG04
  4189.  
  4190. G_M60652_IG03: ; offs=00002CH, size=0005H, bbWeight=0.50 PerfScore 0.50, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
  4191.  
  4192. IN0003: 00002C call CORINFO_HELP_DBG_IS_JUST_MY_CODE
  4193.  
  4194. G_M60652_IG04: ; offs=000031H, size=0017H, bbWeight=1 PerfScore 9.83, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  4195.  
  4196. IN0004: 000031 nop
  4197. IN0005: 000032 vxorps xmm0, xmm0
  4198. IN0006: 000036 vmovapd xmmword ptr [V01 rbp-10H], xmm0
  4199. IN0007: 00003B vmovapd xmm0, xmmword ptr [V01 rbp-10H]
  4200. IN0008: 000040 vmovapd xmmword ptr [V02 rbp-20H], xmm0
  4201. IN0009: 000045 nop
  4202. IN000a: 000046 jmp SHORT G_M60652_IG05
  4203.  
  4204. G_M60652_IG05: ; offs=000048H, size=0011H, bbWeight=1 PerfScore 8.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
  4205.  
  4206. IN000b: 000048 mov rax, bword ptr [V00 rbp+10H]
  4207. IN000c: 00004C vmovapd xmm0, xmmword ptr [V02 rbp-20H]
  4208. IN000d: 000051 vmovupd xmmword ptr [rax], xmm0
  4209. IN000e: 000055 mov rax, bword ptr [V00 rbp+10H]
  4210.  
  4211. G_M60652_IG06: ; offs=000059H, size=0006H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend
  4212.  
  4213. IN0019: 000059 lea rsp, [rbp]
  4214. IN001a: 00005D pop rbp
  4215. IN001b: 00005E ret
  4216.  
  4217. Unwind Info:
  4218. >> Start offset : 0x000000 (not in unwind data)
  4219. >> End offset : 0x00005f (not in unwind data)
  4220. Version : 1
  4221. Flags : 0x00
  4222. SizeOfProlog : 0x05
  4223. CountOfUnwindCodes: 2
  4224. FrameRegister : none (0)
  4225. FrameOffset : N/A (no FrameRegister) (Value=0)
  4226. UnwindCodes :
  4227. CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 7 * 8 + 8 = 64 = 0x40
  4228. CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
  4229. allocUnwindInfo(pHotCode=0x00007FFF50DC7D80, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x5f, unwindSize=0x8, pUnwindBlock=0x000002279AC8B040, funKind=0 (main function))
  4230. *************** In genIPmappingGen()
  4231. IP mapping count : 8
  4232. IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
  4233. IL offs NO_MAP : 0x00000023 ( STACK_EMPTY )
  4234. IL offs 0x0000 : 0x00000031 ( STACK_EMPTY )
  4235. IL offs 0x0001 : 0x00000032 ( STACK_EMPTY )
  4236. IL offs 0x0009 : 0x0000003B ( STACK_EMPTY )
  4237. IL offs 0x000B : 0x00000045 ( STACK_EMPTY )
  4238. IL offs 0x000D : 0x00000048 ( STACK_EMPTY )
  4239. IL offs EPILOG : 0x00000059 ( STACK_EMPTY )
  4240.  
  4241. *************** In genSetScopeInfo()
  4242. VarLocInfo count is 4
  4243. *************** Variable debug info
  4244. 4 live ranges
  4245. -2( retBuff) : From 00000000h to 00000023h, in rcx
  4246. 0( UNKNOWN) : From 00000031h to 00000059h, in rbp[-16] (1 slot)
  4247. 1( UNKNOWN) : From 00000031h to 00000059h, in rbp[-32] (1 slot)
  4248. -2( retBuff) : From 00000031h to 00000059h, in rbp[16] (1 slot)
  4249. *************** In gcInfoBlockHdrSave()
  4250. Set code length to 95.
  4251. Set ReturnKind to Scalar.
  4252. Set stack base register to rbp.
  4253. Set Outgoing stack arg area size to 32.
  4254. Stack slot id for offset 16 (0x10) (frame) (byref, untracked) = 0.
  4255. Register slot id for reg rax (byref) = 1.
  4256. Set state of slot 1 at instr offset 0x4c to Live.
  4257. Set state of slot 1 at instr offset 0x5f to Dead.
  4258. Defining interruptible range: [0x23, 0x59).
  4259. Method code size: 95
  4260.  
  4261. Allocations for CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double] (MethodHash=f5b01313)
  4262. count: 326, size: 31385, max = 2640
  4263. allocateMemory: 65536, nraUsed: 33832
  4264.  
  4265. Alloc'd bytes by kind:
  4266. kind | size | pct
  4267. ---------------------+------------+--------
  4268. AssertionProp | 0 | 0.00%
  4269. ASTNode | 4400 | 14.02%
  4270. InstDesc | 3908 | 12.45%
  4271. ImpStack | 384 | 1.22%
  4272. BasicBlock | 2224 | 7.09%
  4273. fgArgInfo | 0 | 0.00%
  4274. fgArgInfoPtrArr | 0 | 0.00%
  4275. FlowList | 192 | 0.61%
  4276. TreeStatementList | 0 | 0.00%
  4277. SiScope | 264 | 0.84%
  4278. DominatorMemory | 0 | 0.00%
  4279. LSRA | 3260 | 10.39%
  4280. LSRA_Interval | 440 | 1.40%
  4281. LSRA_RefPosition | 1920 | 6.12%
  4282. Reachability | 0 | 0.00%
  4283. SSA | 0 | 0.00%
  4284. ValueNumber | 0 | 0.00%
  4285. LvaTable | 1920 | 6.12%
  4286. UnwindInfo | 0 | 0.00%
  4287. hashBv | 120 | 0.38%
  4288. bitset | 56 | 0.18%
  4289. FixedBitVect | 8 | 0.03%
  4290. Generic | 1306 | 4.16%
  4291. LocalAddressVisitor | 0 | 0.00%
  4292. FieldSeqStore | 0 | 0.00%
  4293. ZeroOffsetFieldMap | 40 | 0.13%
  4294. ArrayInfoMap | 0 | 0.00%
  4295. MemoryPhiArg | 0 | 0.00%
  4296. CSE | 0 | 0.00%
  4297. GC | 2416 | 7.70%
  4298. CorSig | 0 | 0.00%
  4299. Inlining | 120 | 0.38%
  4300. ArrayStack | 0 | 0.00%
  4301. DebugInfo | 376 | 1.20%
  4302. DebugOnly | 6724 | 21.42%
  4303. Codegen | 1128 | 3.59%
  4304. LoopOpt | 0 | 0.00%
  4305. LoopHoist | 0 | 0.00%
  4306. Unknown | 107 | 0.34%
  4307. RangeCheck | 0 | 0.00%
  4308. CopyProp | 0 | 0.00%
  4309. SideEffects | 0 | 0.00%
  4310. ObjectAllocator | 0 | 0.00%
  4311. VariableLiveRanges | 0 | 0.00%
  4312. ClassLayout | 72 | 0.23%
  4313. TailMergeThrows | 0 | 0.00%
  4314.  
  4315. ****** DONE compiling CoreLab.Program:Callee():System.Runtime.Intrinsics.Vector128`1[Double]
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!