Lab #2 - Top.vhd (Dean Nguyen)

--Lab #2: Top (Dean Nguyen)--

--Libraries--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

--Entity--
ENTITY Top IS
    GENERIC (   SIZE                : INTEGER   := 8); --Generic with default value
    PORT        (   CLK, RESET_N    : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
                    INPUT               : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Random seed input
                    OUTPUT          : OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0)); --Output
END Top;

--Architecture--
ARCHITECTURE behavioral OF Top IS

--Components--
COMPONENT Shift_Reg
    GENERIC (   SIZE                                    : INTEGER   := 8); --Generic with default value
    PORT        (   CLK, RESET_N, LOAD, SERIAL_IN   : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
                    SEED                                    : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Random seed input
                    PARALLEL_OUT                        : OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0)); --Output
END COMPONENT;

COMPONENT XOR_Gate
    GENERIC (   SIZE        : INTEGER   := 8); --Generic with default value
    PORT        (   INPUT       : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Input by # of inputs
                    OUTPUT  : OUT STD_LOGIC); --Output
END COMPONENT;

--Inputs--
SIGNAL CLK_Top              : STD_LOGIC;
SIGNAL RESET_N_Top      : STD_LOGIC;
SIGNAL LOAD_Top         : STD_LOGIC;
SIGNAL SERIAL_IN_Top        : STD_LOGIC;
SIGNAL SEED_Top         : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL INPUT_TOP            : STD_LOGIC_VECTOR(1 DOWNTO 0);

--Outputs--
SIGNAL PARALLEL_OUT_Top : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL OUTPUT_Top           : STD_LOGIC;

BEGIN

    CLK_Top <= CLK;
    RESET_N_Top <= RESET_N;
    SEED_Top <= INPUT;
    PARALLEL_OUT_Top <= OUTPUT;

    uut: Shift_Reg
        GENERIC MAP (
            SIZE => 10)
        PORT MAP (
            CLK => CLK_Top,
            RESET_N => RESET_N_Top,
            LOAD => LOAD_Top,
            SERIAL_IN => SERIAL_IN_Top,
            SEED => SEED_Top,
            PARALLEL_OUT => PARALLEL_OUT_Top);

    uut: XOR_Gate
        GENERIC MAP (
            SIZE => 2)
        PORT MAP (
            INPUT => INPUT_Top,
            OUTPUT => OUTPUT_Top);