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  1. /*
  2.  * File:   main.c
  3.  * Author: user
  4.  *
  5.  * Created on 13 ??????? 2019 ?., 10:10
  6.  */
  7.  
  8. // PIC18F4525 Configuration Bit Settings
  9.  
  10. // 'C' source line config statements
  11.  
  12.  
  13. // PIC18F4525 Configuration Bit Settings
  14.  
  15. // 'C' source line config statements
  16.  
  17.  
  18. // PIC18F4525 Configuration Bit Settings
  19.  
  20. // 'C' source line config statements
  21.  
  22. // CONFIG1H
  23. #pragma config OSC = HSPLL      // Oscillator Selection bits (HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1))
  24. #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  25. #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
  26.  
  27. // CONFIG2L
  28. #pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
  29. #pragma config BOREN = ON       // Brown-out Reset Enable bits (Brown-out Reset enabled and controlled by software (SBOREN is enabled))
  30. #pragma config BORV = 3         // Brown Out Reset Voltage bits (Minimum setting)
  31.  
  32. // CONFIG2H
  33. #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
  34. #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
  35.  
  36. // CONFIG3H
  37. #pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
  38. #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
  39. #pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
  40. #pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
  41.  
  42. // CONFIG4L
  43. #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
  44. #pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
  45. #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
  46.  
  47. // CONFIG5L
  48. #pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-003FFFh) not code-protected)
  49. #pragma config CP1 = OFF        // Code Protection bit (Block 1 (004000-007FFFh) not code-protected)
  50. #pragma config CP2 = OFF        // Code Protection bit (Block 2 (008000-00BFFFh) not code-protected)
  51.  
  52. // CONFIG5H
  53. #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
  54. #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
  55.  
  56. // CONFIG6L
  57. #pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-003FFFh) not write-protected)
  58. #pragma config WRT1 = OFF       // Write Protection bit (Block 1 (004000-007FFFh) not write-protected)
  59. #pragma config WRT2 = OFF       // Write Protection bit (Block 2 (008000-00BFFFh) not write-protected)
  60.  
  61. // CONFIG6H
  62. #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
  63. #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
  64. #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
  65.  
  66. // CONFIG7L
  67. #pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
  68. #pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
  69. #pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
  70.  
  71. // CONFIG7H
  72. #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
  73.  
  74. // #pragma config statements should precede project file includes.
  75. // Use project enums instead of #define for ON and OFF.
  76. #define _XTAL_FREQ 40000000
  77. #include <xc.h>
  78. #include <stdio.h>
  79. #include <stdlib.h>
  80.  
  81. unsigned char cnt;
  82.  
  83. void check_delay(int time)        
  84. {
  85.  
  86.     int i = 0;
  87.     for(i = 0; i < time/20; i++)
  88.     {
  89.         __delay_ms(20);
  90.  
  91.         if(PORTBbits.RB0 == 0)
  92.         {
  93.             __delay_ms(10);            
  94.             while(PORTBbits.RB0 == 0);     
  95.             cnt++;
  96.             __delay_ms(10);            
  97.             break;
  98.            
  99.         }
  100.     }
  101. }
  102.  
  103.  
  104. unsigned char check_cnt()
  105. {
  106.    
  107.     if(PORTBbits.RB0 == 0)          
  108.     {
  109.  
  110.         if(PORTBbits.RB0 == 0)
  111.         {
  112.             __delay_ms(10);            
  113.             while(PORTBbits.RB0 == 0);     
  114.             cnt++;
  115.             __delay_ms(10);            
  116.            
  117.         }
  118.     }
  119.     return (cnt);
  120. }
  121.  
  122. void sound_delay()
  123. {
  124.     int i = 0;
  125.     for(i = 0; i < 2000; i++)
  126.             {
  127.                 if(check_cnt() == 3)
  128.                     break;
  129.                 LATCbits.LATC0 = 1;
  130.                 __delay_us(80);
  131.                 LATCbits.LATC0 = 0;
  132.                 __delay_us(80);
  133.             }
  134.    
  135. }
  136.  
  137. int main()
  138. {
  139.     TRISC0 = 0;
  140.     TRISB0 = 1;
  141.     TRISB3 = 0;  
  142.     int i = 0;
  143.     cnt = 0;
  144.     LATBbits.LATB3 = 0;
  145.    
  146.     while (1)
  147.     {
  148.         if(PORTBbits.RB0==0)
  149.         {
  150.             __delay_ms(10);            
  151.             while(PORTBbits.RB0==0);   
  152.             cnt++;
  153.             __delay_ms(10);            
  154.         }
  155.        
  156.         switch (cnt)
  157.         {
  158.             case 1:  
  159.             LATBbits.LATB3 = 1;
  160.             check_delay(200);
  161.             LATBbits.LATB3 = 0;
  162.             if(cnt == 1)        
  163.             {
  164.                 check_delay(200);
  165.             }
  166.             break;
  167.            
  168.             case 2:
  169.             LATBbits.LATB3 = 1;  
  170.             sound_delay();
  171.             LATBbits.LATB3 = 0;
  172.            
  173.             if(cnt == 2)
  174.             {
  175.                 sound_delay();
  176.             }
  177.             break;
  178.        
  179.             case 3:
  180.             cnt=0;
  181.             break;      
  182.        
  183.             default:
  184.             cnt=0;
  185.             break;
  186.         }
  187.     }      
  188.    
  189.     return (EXIT_SUCCESS);
  190. }
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