SHARE
TWEET

Untitled

a guest Jun 19th, 2019 78 Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    11:45:48 05/21/2019
  6. -- Design Name:
  7. -- Module Name:    mux4na1 - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity mux4na1 is
  33.     Port ( wejscie : in  STD_LOGIC_VECTOR (1 downto 0);
  34.            s0 : in  STD_LOGIC_VECTOR (3 downto 0);
  35.            s1 : in  STD_LOGIC_VECTOR (3 downto 0);
  36.            s2 : in  STD_LOGIC_VECTOR (3 downto 0);
  37.            s3 : in  STD_LOGIC_VECTOR (3 downto 0);
  38.            wyjscie : out  STD_LOGIC_VECTOR (3 downto 0));
  39. end mux4na1;
  40.  
  41. architecture Behavioral of mux4na1 is
  42.  
  43. begin
  44.  
  45. with wejscie select
  46.     wyjscie <= s0 when "00",
  47.                   s1 when "01",
  48.                   s2 when "10",
  49.                   s3 when others;
  50.  
  51.  
  52. end Behavioral;
RAW Paste Data
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy. OK, I Understand
 
Top