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Jun 27th, 2017
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VHDL 0.85 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_unsigned;
  4.  
  5. entity debouncer is
  6.     generic( N:integer := 19200000); --19200000
  7.     port
  8.     (
  9.         clk: in std_logic;
  10.         sin: in std_logic;
  11.         output: out std_logic;
  12.         --brj: out integer range 0 to 20000000
  13.     );
  14. end debouncer;
  15.  
  16. architecture arh of debouncer is
  17.     signal brojac,brojac2: integer range 0 to 20000000;
  18.     signal flag: std_logic;
  19.     begin
  20.         process(clk)
  21.         begin
  22.             if clk='1' then
  23.                 if sin='1' then
  24.                     brojac<=0;
  25.                 elsif brojac /= N and sin='0' and flag='0' then
  26.                     brojac<=brojac+1;
  27.                 elsif brojac=N then
  28.                     flag<='1';
  29.                     brojac<=0;
  30.                 end if;
  31.                 if flag = '1' then
  32.                     brojac2<=brojac2+1;
  33.                     output<='1';
  34.                 end if;
  35.                 if brojac2=N then
  36.                     flag<='0';
  37.                     brojac2<=0;
  38.                     output<='0';
  39.                 end if;
  40.             end if;
  41.             --brj<=brojac;
  42.         end process;
  43. end arh;
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