module simulare();
    reg x,t,y,clear,load,clk;
    wire z;
    final pipeline(x,t,y,z,clear,load,clk);
    initial begin
        x = 1; t = 1; y = 1;  clear = 0; load = 1; clk = 0;
        #50 x = 1; t = 0; y = 1; clear = 0; load = 1; clk = 1;
        #50 x = 1; t = 0; y = 1; clear = 0; load = 1; clk = 0;
        #50 x = 1; t = 0; y = 1;  clear = 0; load = 1; clk = 1;
        #50 x = 0; t = 0; y = 0; clear = 0; load = 1; clk = 0;
        #50 x = 1; t = 1; y = 1; clear = 0; load = 1; clk = 1;
        #50 x = 1; t = 0; y = 1; clear = 0; load = 1; clk = 0;
        #50 x = 1; t = 0; y = 1;  clear = 0; load = 1; clk = 1;
        #50 x = 1; t = 1; y = 0; clear = 0; load = 1; clk = 0;

    end

    always #50 clk =~clk;

endmodule