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- Library Ieee ;
- USE Ieee.std_logic_1164.all ;
- USE ieee.numeric_std.all;
- use ieee.std_logic_unsigned.all;
- ENTITY Lab7 IS
- PORT ( A : in STD_LOGIC_VECTOR(3 downto 0); --A input
- B : in STD_LOGIC_VECTOR(3 downto 0); --B input
- Op : in STD_LOGIC_VECTOR(1 downto 0); --Selects operation
- hex0,hex1, hex2, hex3 : out STD_LOGIC_VECTOR(6 downto 0) --hex displays
- );
- END Lab7;
- ARCHITECTURE structure OF Lab7 IS
- SIGNAL in_num_signal: STD_LOGIC_VECTOR(7 DOWNTO 0):= "00000000" ;
- ---------------------------------------------------------------------
- COMPONENT Lab5 is
- Port ( A : in STD_LOGIC_VECTOR(3 downto 0); --A input
- B : in STD_LOGIC_VECTOR(3 downto 0); --B input
- Op : in STD_LOGIC_VECTOR(1 downto 0);
- R : out STD_LOGIC_VECTOR(7 downto 0));
- END COMPONENT;
- ---------------------------------------------------------------------
- COMPONENT Lab6 IS
- PORT ( in_num : in STD_LOGIC_VECTOR(7 downto 0); --8-bit input
- HEX0,HEX1,HEX2,HEX3 : out STD_LOGIC_VECTOR(6 downto 0));
- End COMPONENT Lab6;
- ---------------------------------------------------------------------
- BEGIN
- Calculator : Lab5
- PORT MAP (A => A,
- B => B,
- Op => Op);
- DisplayDriver : Lab6
- PORT MAP (HEX0 => hex0,
- HEX1 => hex1,
- HEX2 => hex2,
- HEX3 => hex3,
- in_num => in_num_signal);
- END structure;
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