library ieee;
use ieee.std_logic_1164.all;

entity Temporizador is
generic(ClockFrequency : integer);
port(
	enable	: in std_logic; -- si enable = 1 funciona
	clk 	: in std_logic;
	nrst 	: in std_logic; -- rst cuando = 0
	segundos: inout integer;
	minutos : inout integer;
	max 	: inout std_logic
	);
end entity;

architecture rtl of Temporizador is
begin

	component divisor is
		Port (
			clk_in : in  STD_LOGIC;
			clk_out: out STD_LOGIC
			);
	end component;
	signal nclock: std_logic;

	process(clk) is
	begin
		div: divisor
			port map(
				clk_in => clk,
				clk_out => nclk
			);

		if rising_edge(nclk) then
			if nrst = '0'  then
			segundos <= 0;
			minutos <= 0;
			max <= '0';

			else
				--verdadero cada minuto
				if segundos =59 then
					segundos <= 0;

					if minutos = 1 then
						segundos <= 0;
						minutos <= 0;
						max <= '1';
					else
						minutos <= minutos +1;
					end if;
				else
					segundos <= segundos + 1;
				end if;

			end if;
		end if;
	end process;
end architecture;