uc2

--Przypisanie warunkowe	 Y <= A when S = '0' else B; Y <= A when S = '0' else 	 B when S = '2' else 'X'; --Przypisanie selektywne Y <= A when "00", 	 B when "01", 	 "XX" when others; --Dekoder 1 z 4 na BIN za pomocą przypisania warunkowego 	library IEEE; 	use IEEE.std_logic_1164.all; 	entity UC2_002_Lab1_Dekoder1z4naBINwarunkowe is 		 port( 			 A : in STD_LOGIC_VECTOR(3 downto 0); 			 Y : out STD_LOGIC_VECTOR(1 downto 0) 		 ); 	end UC2_002_Lab1_Dekoder1z4naBINwarunkowe; --}} End of automatically maintained section 	 	architecture UC2_002_Lab1_Dekoder1z4naBINwarunkowe of UC2_002_Lab1_Dekoder1z4naBINwarunkowe is 	begin	-- enter your statements here -- 		 		Y <= "00" when (A = "0001") else	 			 "01" when (A = "0010") else 			 "10" when (A = "0100") else 			 "11" when (A = "1000") else 			 "XX"; 	end UC2_002_Lab1_Dekoder1z4naBINwarunkowe; --Dekoder 1 z 4 na BIN za pomocą przypisania selektywnego 	library IEEE; 	use IEEE.std_logic_1164.all; 	entity UC2_002_Lab1_Dekoder1z4naBINselektywne is 		 port( 			 A : in STD_LOGIC_VECTOR(3 downto 0); 			 Y : out STD_LOGIC_VECTOR(1 downto 0) 		 ); 	end UC2_002_Lab1_Dekoder1z4naBINselektywne; --}} End of automatically maintained section 	 	architecture UC2_002_Lab1_Dekoder1z4naBINselektywne of UC2_002_Lab1_Dekoder1z4naBINselektywne is 	begin	-- enter your statements here -- 		with A select 		Y <= "00" when "0001",	 			 "01" when "0010", 			 "10" when "0100", 			 "11" when "1000", 			 "XX" when others; 	end UC2_002_Lab1_Dekoder1z4naBINselektywne; 	 	 	 	 	 	 	 	 --Dekoder BIN na 1 z 4 za pomocą przypisania selektywnego 	library IEEE; 	use IEEE.std_logic_1164.all; 	entity UC2_002_Lab1_DekoderBINna1z4selektywne is 		 port( 			 A : in STD_LOGIC_VECTOR(1 downto 0); 			 Y : out STD_LOGIC_VECTOR(3 downto 0) 		 ); 	end UC2_002_Lab1_DekoderBINna1z4selektywne; --}} End of automatically maintained section 	 	architecture UC2_002_Lab1_DekoderBINna1z4selektywne of UC2_002_Lab1_DekoderBINna1z4selektywne is 	begin	-- enter your statements here -- 		with A select 		Y <= "0001" when "00",	 			 "0010" when "01", 			 "0100" when "10", 			 "1000" when "11", 			 "0000" when others; 	end UC2_002_Lab1_DekoderBINna1z4selektywne; --Układ kombinacyjny, gdzie prawda dla (1, 3, 7, 9, 14, 15)	 	library IEEE; 	use IEEE.std_logic_1164.all; 	entity Kombinacyjny_true_1_3_7_9_14_15 is 		 port( 			 A : in STD_LOGIC_VECTOR(6 downto 0); 			 Y : out STD_LOGIC 		 ); 	end Kombinacyjny_true_1_3_7_9_14_15; --}} End of automatically maintained section 	 	architecture Kombinacyjny_true_1_3_7_9_14_15 of Kombinacyjny_true_1_3_7_9_14_15 is 	begin	-- enter your statements here -- 		with A select 		Y <= '1' when 1 | 3 | 7 | 9 | 14 | 15,	 			 '0' when others; 	end Kombinacyjny_true_1_3_7_9_14_15; 	 	 						 --Układ kombinacyjny, gdzie prawda dla (1, 3, 7, 9, 14, 15) 	entity mux4 is 		port (A : in std_logic_vector(3 downto 0); 			 Y : out std_logic 			 ); 	end mux4; 	architecture a1 of mux4 is 	begin 		with A select 		Y <= '1' when "0001",--1 			 '1' when "0011",--3 			 '1' when "0111",--7 			 '1' when "1001",--9 			 '1' when "1110",--14 			 '1' when "1111",--15 			 '0' when others; 	end a1; --multiplexer 4 wejściowy (więc linia adresowa 2 bitowa) 	entity mux4 is 		port (A,B,C,D : in std_logic); 				 adr : in std_logic_vector(1 downto 0); 					Y : out std_logic); 	end mux4; 	architecture a1 of mux4 is 	begin 		with adr select 		Y <= A when "00", 			 B when "01", 			 C when "10", 			 D when others; 	end a1; --Sterowanie wyświetlaczem 7-segmentowym 	entity wys is 	port(a : in std_logic_vector(3 downto 0); 		 y : out std_logic_vector(6 downto 0); 	end wys 	archirecture a1 of wys is 	begin 	with a select 	y<= "0000011" when "0001", 		"1101101" when "0010", 		"1100111" when "0011", 		"1010011" when "0100",	 		"1110110" when "0101", 		"1111110" when "0110", 		"0100011" when "0111", 		"1111111" when "1000", 		"1110111" when "1001",	 		"0111111" when "0000", 		"0000000" when others; 	end a1 --Licznik modulo 10 	library IEEE; 	use IEEE.std_logic_1164.all; 	use.IEEE.numeric_std.all; 	entity mod10 is 		port(C,R : in std_logic; 		Q : out std_logic_vector(3 downto 0)); 	end mod10; 	architecture mod10 of mod10 is 	begin 		process(C,R) 		variable cnt : unsigned(3 downto 0); 		begin 			if R='1' then 				cnt := "0000"; 			elsif rising_edge(C) then 				if cnt<9 then 					cnt := cnt + 1; 				else 					cnt := "0000"; 				end if; 			end if; 			Q <= std_logic_vector(cnt); 		end process; 	end mod10; --Licznik modulo 16 	library IEEE; 	use IEEE.std_logic_1164.all; 	use.IEEE.numeric_std.all; 	entity mod10 is 		port(C,R : in std_logic; 		Q : out std_logic_vector(4 downto 0)); 	end mod10; 	architecture mod10 of mod10 is 	begin 		process(C,R) 		variable cnt : unsigned(3 downto 0); 		begin 			if R='1' then 				cnt := "0000"; 			elsif rising_edge(C) then 				if cnt<15 then 					cnt := cnt + 1; 				else 					cnt := "0000"; 				end if; 			end if; 			Q <= std_logic_vector(cnt); 		end process; 	end mod10;