`timescale 1ns / 1ps

/* 3-bit shift register */
module character_recognition (
        // Clock (positive edge polarity)
        input clk,

        // Reset (active-high synchronous)
        input reset,

        // Update (rising edge synchronous)
        input update,

        // Input
        input [2:0] character,

        // Outputs
        output finished,
        output valid_sequence
    );

    localparam  start = 3'b000,
                invalid = 3'b001,
                square_open = 3'b010,
                round_open = 3'b011,
                round_closed = 3'b100,
                valid = 3'b101;


    reg [2:0] cur_state;
    reg [2:0] next_state;
    reg prev_update;

    always @(posedge clk)
    begin
    cur_state <= next_state;
    prev_update <= update;
    end

    always @(*)
    begin
        if(reset) next_state = start;
        else if(update&&prev_update!=update)
        begin
            case(cur_state)
                start: next_state=(character == 3'b001)?square_open:invalid;
                square_open: next_state=(character == 3'b010)?round_open:invalid;
                round_open:begin
                            if(character == 3'b000) next_state = round_open;
                            else if(character == 3'b011) next_state = round_closed;
                            else next_state = invalid;
                        end
                round_closed: next_state=(character == 3'b100)?valid:invalid;
                valid: next_state =valid;

                default: next_state = start;
            endcase
        end
    end

    assign finished = (cur_state == valid || cur_state == invalid);
    assign valid_sequence = (cur_state == valid);
endmodule