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  1. open_project /home/lutrampal/cours/s5/implem_sle/light_wrapper_64_128_pcd_optr/light_wrapper_64_128_pcd_optr.xpr
  2. Scanning sources...
  3. Finished scanning sources
  4. INFO: [IP_Flow 19-234] Refreshing IP repositories
  5. INFO: [IP_Flow 19-1704] No user IP repositories specified
  6. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
  7. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
  8. update_compile_order -fileset sources_1
  9. reset_run synth_1
  10. launch_runs synth_1 -jobs 4
  11. [Sun Feb  3 18:30:17 2019] Launched synth_1...
  12. Run output will be captured here: /home/lutrampal/cours/s5/implem_sle/light_wrapper_64_128_pcd_optr/light_wrapper_64_128_pcd_optr.runs/synth_1/runme.log
  13. open_run synth_1 -name synth_1
  14. Design is defaulting to impl run constrset: constrs_1
  15. Design is defaulting to synth run part: xc7z020clg400-1
  16. INFO: [Netlist 29-17] Analyzing 198 Unisim elements for replacement
  17. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  18. INFO: [Project 1-479] Netlist was created with Vivado 2018.2
  19. INFO: [Project 1-570] Preparing netlist for logic optimization
  20. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  21. INFO: [Project 1-111] Unisim Transformation Summary:
  22. No Unisim elements were transformed.
  23.  
  24. write_verilog /home/lutrampal/light_wrapper_64_128_pcd_optr.v
  25. close_project
  26. create_project project_3 /home/lutrampal/tmp/project_3 -part xc7z010clg400-1
  27. INFO: [IP_Flow 19-234] Refreshing IP repositories
  28. INFO: [IP_Flow 19-1704] No user IP repositories specified
  29. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.2/data/ip'.
  30. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
  31. set_property target_language VHDL [current_project]
  32. set_property simulator_language VHDL [current_project]
  33. add_files -norecurse {/media/data/git/simon_bist/generated_arch/light_wrapper_64_128_pcd_optr/vhd/constants.vhd /media/data/git/simon_bist/generated_arch/light_wrapper_64_128_pcd_optr/vhd/cryptoProc_tb.vhd /home/lutrampal/light_wrapper_64_128_pcd_optr.v}
  34. update_compile_order -fileset sources_1
  35. launch_simulation
  36. INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/lutrampal/tmp/project_3/project_3.sim/sim_1/behav/xsim'
  37. INFO: [SIM-utils-51] Simulation object is 'sim_1'
  38. INFO: [SIM-utils-54] Inspecting design source files for 'cryptoProc_tb' in fileset 'sim_1'...
  39. INFO: [USF-XSim-97] Finding global include files...
  40. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
  41. INFO: [USF-XSim-2] XSim::Compile design
  42. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/lutrampal/tmp/project_3/project_3.sim/sim_1/behav/xsim'
  43. xvlog --incr --relax -prj cryptoProc_tb_vlog.prj
  44. INFO: [VRFC 10-2263] Analyzing Verilog file "/home/lutrampal/light_wrapper_64_128_pcd_optr.v" into library xil_defaultlib
  45. INFO: [VRFC 10-311] analyzing module FSM
  46. INFO: [VRFC 10-311] analyzing module cryptoProc
  47. INFO: [VRFC 10-311] analyzing module cryptoProcWithBIST
  48. INFO: [VRFC 10-311] analyzing module keyGenerator
  49. INFO: [VRFC 10-311] analyzing module keyMemory
  50. INFO: [VRFC 10-311] analyzing module msgRegister
  51. INFO: [VRFC 10-2263] Analyzing Verilog file "/home/lutrampal/tmp/project_3/project_3.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
  52. INFO: [VRFC 10-311] analyzing module glbl
  53. xvhdl --incr --relax -prj cryptoProc_tb_vhdl.prj
  54. INFO: [VRFC 10-163] Analyzing VHDL file "/media/data/git/simon_bist/generated_arch/light_wrapper_64_128_pcd_optr/vhd/constants.vhd" into library xil_defaultlib
  55. INFO: [VRFC 10-163] Analyzing VHDL file "/media/data/git/simon_bist/generated_arch/light_wrapper_64_128_pcd_optr/vhd/cryptoProc_tb.vhd" into library xil_defaultlib
  56. INFO: [VRFC 10-307] analyzing entity cryptoProc_tb
  57. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
  58. INFO: [USF-XSim-3] XSim::Elaborate design
  59. INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/lutrampal/tmp/project_3/project_3.sim/sim_1/behav/xsim'
  60. Vivado Simulator 2018.2
  61. Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
  62. Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto 0252054ec3e04f868ec2d8fa0135ab44 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot cryptoProc_tb_behav xil_defaultlib.cryptoProc_tb xil_defaultlib.glbl -log elaborate.log
  63. Using 8 slave threads.
  64. Starting static elaboration
  65. WARNING: [VRFC 10-278] actual bit length 14 differs from formal bit length 16 for port DOBDO [/home/lutrampal/light_wrapper_64_128_pcd_optr.v:4873]
  66. Completed static elaboration
  67. Starting simulation data flow analysis
  68. Completed simulation data flow analysis
  69. Time Resolution for simulation is 1ps
  70. Compiling package std.standard
  71. Compiling package std.textio
  72. Compiling package ieee.std_logic_1164
  73. Compiling package ieee.numeric_std
  74. Compiling package xil_defaultlib.constants
  75. Compiling package vl.vl_types
  76. Compiling module xil_defaultlib.glbl
  77. Compiling module unisims_ver.GND
  78. Compiling module unisims_ver.VCC
  79. Compiling module unisims_ver.IBUF
  80. Compiling module unisims_ver.BUFG
  81. Compiling module unisims_ver.LUT5
  82. Compiling module unisims_ver.LUT4
  83. Compiling module unisims_ver.x_lut3_mux8
  84. Compiling module unisims_ver.LUT3
  85. Compiling module unisims_ver.LUT6
  86. Compiling module unisims_ver.x_lut2_mux4
  87. Compiling module unisims_ver.LUT2
  88. Compiling module unisims_ver.FDSE_default
  89. Compiling module unisims_ver.FDRE_default
  90. Compiling module xil_defaultlib.FSM
  91. Compiling module xil_defaultlib.keyGenerator
  92. Compiling module unisims_ver.RB18_INTERNAL_VLOG(READ_WIDTH_A=...
  93. Compiling module unisims_ver.RAMB18E1(READ_WIDTH_A=18,READ_WI...
  94. Compiling module xil_defaultlib.keyMemory
  95. Compiling module unisims_ver.FDCE_default
  96. Compiling module xil_defaultlib.msgRegister
  97. Compiling module xil_defaultlib.cryptoProc
  98. Compiling module unisims_ver.OBUF
  99. Compiling module xil_defaultlib.cryptoProcWithBIST
  100. Compiling architecture behavior of entity xil_defaultlib.cryptoproc_tb
  101. Built simulation snapshot cryptoProc_tb_behav
  102.  
  103. ****** Webtalk v2018.2 (64-bit)
  104.   **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  105.   **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
  106.     ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
  107.  
  108. source /home/lutrampal/tmp/project_3/project_3.sim/sim_1/behav/xsim/xsim.dir/cryptoProc_tb_behav/webtalk/xsim_webtalk.tcl -notrace
  109. INFO: [Common 17-186] '/home/lutrampal/tmp/project_3/project_3.sim/sim_1/behav/xsim/xsim.dir/cryptoProc_tb_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sun Feb  3 18:35:23 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html.
  110. INFO: [Common 17-206] Exiting Webtalk at Sun Feb  3 18:35:23 2019...
  111. run_program: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 7708.039 ; gain = 0.000 ; free physical = 1186 ; free virtual = 5541
  112. INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
  113. INFO: [USF-XSim-4] XSim::Simulate design
  114. INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/lutrampal/tmp/project_3/project_3.sim/sim_1/behav/xsim'
  115. INFO: [USF-XSim-98] *** Running xsim
  116.    with args "cryptoProc_tb_behav -key {Behavioral:sim_1:Functional:cryptoProc_tb} -tclbatch {cryptoProc_tb.tcl} -log {simulate.log}"
  117. INFO: [USF-XSim-8] Loading simulator feature
  118. Vivado Simulator 2018.2
  119. Time resolution is 1 ps
  120. source cryptoProc_tb.tcl
  121. # set curr_wave [current_wave_config]
  122. # if { [string length $curr_wave] == 0 } {
  123. #   if { [llength [get_objects]] > 0} {
  124. #     add_wave /
  125. #     set_property needs_save false [current_wave_config]
  126. #   } else {
  127. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
  128. #   }
  129. # }
  130. # run 1000ns
  131. Note: starting Simon 64/128 test ...
  132. Time: 20 ns  Iteration: 0  Process: /cryptoProc_tb/stim_proc  File: /media/data/git/simon_bist/generated_arch/light_wrapper_64_128_pcd_optr/vhd/cryptoProc_tb.vhd
  133. Note: test BIST...
  134. Time: 20 ns  Iteration: 0  Process: /cryptoProc_tb/stim_proc  File: /media/data/git/simon_bist/generated_arch/light_wrapper_64_128_pcd_optr/vhd/cryptoProc_tb.vhd
  135. INFO: [USF-XSim-96] XSim completed. Design snapshot 'cryptoProc_tb_behav' loaded.
  136. INFO: [USF-XSim-97] XSim simulation ran for 1000ns
  137. launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 7708.039 ; gain = 0.000 ; free physical = 1181 ; free virtual = 5536
  138. llength [  get_objects -r -filter {type != constant} ]
  139. 542
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