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Part 3

a guest Apr 23rd, 2019 111 Never
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.NUMERIC_STD.ALL;
  4.  
  5. entity top is
  6.     Port ( sw : in STD_LOGIC_VECTOR (7 downto 0);
  7.            btnR : in STD_LOGIC;
  8.            btnL : in STD_LOGIC;
  9.            clk : in STD_LOGIC;
  10.            led : out STD_LOGIC_VECTOR(15 downto 0));
  11. end top;
  12.  
  13. architecture Behavioral of top is
  14.  
  15. component debounce is
  16.   Port ( CLK_100M  : in std_logic;
  17.          SW       : in std_logic;
  18.          sglPulse : out std_logic;
  19.          Sig      : out std_logic);
  20. end component;
  21.  
  22. signal start, check : std_logic;
  23. signal stored: std_logic_vector(7 downto 0);
  24.  
  25. begin
  26.  
  27.     start1: debounce Port Map (CLK_100M=>clk, sw=>btnR, sglPulse=>start);
  28.     check1: debounce Port Map (CLK_100M=>clk, sw=>btnL, sglPulse=>check);
  29.    
  30.     process (start)
  31.         begin
  32.            
  33.             if start = '1' then
  34.                 stored <= sw;
  35.             end if;
  36.  
  37.     end process;
  38.    
  39.     process (check)
  40.         begin
  41.             if check = '1' then
  42.                 if stored = sw then
  43.                     led <= "1000000000000000";
  44.                 else
  45.                     led <= "0000000000000000";
  46.                 end if;
  47.             end if;
  48.          end process;
  49.  
  50. end Behavioral;
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