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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.NUMERIC_STD.ALL;
- entity top is
- Port ( sw : in STD_LOGIC_VECTOR (7 downto 0);
- btnR : in STD_LOGIC;
- btnL : in STD_LOGIC;
- clk : in STD_LOGIC;
- led : out STD_LOGIC_VECTOR(15 downto 0));
- end top;
- architecture Behavioral of top is
- component debounce is
- Port ( CLK_100M : in std_logic;
- SW : in std_logic;
- sglPulse : out std_logic;
- Sig : out std_logic);
- end component;
- signal start, check : std_logic;
- signal stored: std_logic_vector(7 downto 0);
- begin
- start1: debounce Port Map (CLK_100M=>clk, sw=>btnR, sglPulse=>start);
- check1: debounce Port Map (CLK_100M=>clk, sw=>btnL, sglPulse=>check);
- process (start)
- begin
- if start = '1' then
- stored <= sw;
- end if;
- end process;
- process (check)
- begin
- if check = '1' then
- if stored = sw then
- led <= "1000000000000000";
- else
- led <= "0000000000000000";
- end if;
- end if;
- end process;
- end Behavioral;
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