--------------------------------------------------------part4-------------------------------------------------------
---------------------------------------------FLASHES DIGITS ON SEVEN SEG--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity part4 is
    port (  SW   : in std_logic_vector( 17 downto 0 ); --0=T 1=CLEAR
        CLOCK_50 : in std_logic;
        KEY  : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- 0=BIGHTER 1=DIMMER
        LEDR :  out std_logic_vector( 17 downto 0 ); -- SET TO THE RESPECTIVE SWITCH STATE
        HEX0 :  out std_logic_vector( 0 to 6 ) );
end part4;

architecture STRUCTURAL of part4 is

    component counter is
        port (  Enable : in std_logic;
                Reset   : in std_logic;
                CLK     : in std_logic; -- CLK <= CLOCK_50
                DIMVAL  : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
                HEX0    :  out std_logic_vector( 0 to 6 ) );
    end component counter;

    component SevenSeg is
        port (  c   : in std_logic_vector(3 downto 0);
            HEX : out std_logic_vector(0 to 6) );  -- HEX0 7-segment display
    end component SevenSeg;

    SIGNAL BRITE : BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0) := "0000";
begin


                DIMMER: PROCESS (KEY,)
                    IF ( KEY(0) = '0' ) THEN
                    BRITE <= BRITE + 1;
                    ELSIF ( KEY(1) = '0') THEN
                    BRITE <= BRITE - 1;

                BEGIN
                    CASE BRITE IS
                        WHEN "0001" => DIMVAL <= "00011000011010100000";  --100K
                        WHEN "0010" => DIMVAL <= "00110000110101000000";  --200K
                        WHEN "0011" => DIMVAL <= "01001001001111100000";  --300K
                        WHEN "0100" => DIMVAL <= "01100001101010000000";  --400K
                        WHEN "0101" => DIMVAL <= "01111010000100100000";  --500K
                        WHEN "0110" => DIMVAL <= "10010010011111000000";  --600K
                        WHEN "0111" => DIMVAL <= "10101010111001100000";  --700K
                        WHEN "1000" => DIMVAL <= "11000011010100000000";  --800K
                        WHEN "1001" => DIMVAL <= "11011011101110100000";  --900K
                        WHEN OTHERS => DIMVAL <= "11111111111111111111"; --MISTAKE
                    END CASE;
                END PROCESS DECODE;
    LEDR <= SW; --STATE OF SWITCHES
    ----DEFINES THE COUNTER COMPONENT
    COUNT: counter port map ( Enable => SW(0), Reset => SW(1), DIMVAL => DIMVAL, HEX0 => HEX0 );

end STRUCTURAL;

---------------------------------------------------------------part2-----------------------------------------------------------------
---------------------------------------------16-BIT SYNCHRONUS COUNTER WITHOUT FLIP FLOPS--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
    port (  Enable : in std_logic;
            Reset   : in std_logic;
            CLK     : in std_logic; -- 0=CLK
            DIMVAL  : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
            HEX0    :  out std_logic_vector( 0 to 6 ) );
end counter;

architecture STRUCTURAL of counter is

    component SevenSeg is
        port (  c   : in std_logic_vector(3 downto 0);
            HEX : out std_logic_vector(0 to 6) );  -- HEX0 7-segment display
    end component SevenSeg;

    signal  QOUT : std_logic_vector( 3 downto 0 ) :="0000"; --- FOUR BITS
    signal  COUNT : std_logic_vector( 25 downto 0 ) :="00000000000000000000000000"; --- 26 BIT COUNTER - COUNTS TO 50MIL
    signal  COUNT2 : std_logic_vector( 20 downto 0 ) :="00000000000000000000"; --- 20 BIT COUNTER - COUNTS TO 1MIL
    SIGNAL  PMW : STD_LOGIC := '0';
begin
    MIL_50 : process( Reset, CLK )
    begin
        if (Reset = '1') then
            QOUT <= "0000";
            COUNT <= (OTHERS => '0');
        elsif (CLK'EVENT) and (CLK ='1') then
            IF ( COUNT = "10111110101111000001111111") THEN
              COUNT <= (OTHERS => '0');
              if Enable = '1' then
                    IF ( QOUT = "1001") THEN
                        QOUT <= "0000";
                    ELSE QOUT <= QOUT + 1;
                    END IF;
                ELSE QOUT <= QOUT;
                end if;
            ELSE COUNT <= COUNT + 1;
            END IF;
        end if;
    end process MIL_50;

    MIL_1 : process( Reset, CLK )
    begin
        if (Reset = '1') then
            COUNT2 <= (OTHERS => '0');
        elsif (CLK'EVENT) and (CLK ='1') then
            IF ( COUNT2 = "11110100001001000000") THEN --1 MIL COUNT
                COUNT2 <= (OTHERS => '0');
                PWM = '1';
            ELSIF (COUNT2 = DIMVAL) THEN
                    PWM = '0';
                    COUNT2 <= COUNT2  + 1;
            ELSE COUNT2 <= COUNT2 +1;


            ELSE ;
            END IF;
        end if;
    end process MIL_1;

    ----------------------------------------OUTPUT THE 16 BIT OUTPUT TO THE SEVEN SEGMENTS DISPLAYS--------------------------------------
    SS0: SevenSeg port map ( c => QOUT, HEX => HEX0 );

end STRUCTURAL ;


-------------------------------------------------7 SEGMENT DECODER----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity SevenSeg is
    port (  c   : in std_logic_vector(3 downto 0);
        HEX : out std_logic_vector(0 to 6) );  -- HEX0 7-segment display
end SevenSeg;

architecture Behavior of SevenSeg is
begin
    SEG_PROCESS: process (c)
    begin
        case c is
        when "0000"  => HEX <= "0000001"; --0
        when "0001"  => HEX <= "1001111"; --1
        when "0010"  => HEX <= "0010010"; --2
        when "0011"  => HEX <= "0000110"; --3
        when "0100"  => HEX <= "1001100"; --4
        when "0101"  => HEX <= "0100100"; --5
        when "0110"  => HEX <= "0100000"; --6
        when "0111"  => HEX <= "0001111"; --7
        when "1000"  => HEX <= "0000000"; --8
        when "1001"  => HEX <= "0001100"; --9
        -- when "1010"  => HEX <= "0001000"; --A
        -- when "1011"  => HEX <= "1100000"; --B
        -- when "1100"  => HEX <= "0110001"; --C
        -- when "1101"  => HEX <= "1000010"; --D
        -- when "1110"  => HEX <= "0110000"; --E
        -- when "1111"  => HEX <= "0111000"; --F
        when others => HEX <= "1111111"; --ELSE
        end case;
    end process SEG_PROCESS;

end Behavior;