reg [1:0] foo;
reg bar;
always @(posedge clk) begin
	foo = a + b;
	if(|foo)
		bar = 1;
end

(then read foo and bar in another block)

===>

reg [1:0] v_foo;
reg v_bar;
reg [1:0] foo;
reg bar;
always @(posedge clk) begin
	v_foo = a + b;
	if(|v_foo)
		v_bar = 1;
	foo <= v_foo;
	bar <= v_bar;
end

(make sure you use v_* signals _only_ in this block. all VHDL does is enforce this using the "variable" which is really just a process-local signal)