display.vhd

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-- Company:
-- Engineer:
--
-- Create Date:    12:29:51 03/05/2019
-- Design Name:
-- Module Name:    Lab6 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Lab6 is
port(
    signal clk_i : in std_logic;
    signal led7_an_o : out std_logic_vector(3 downto 0);
    signal led7_seg_o : out std_logic_vector(7 downto 0);
    signal sw_i : in std_logic_vector(7 downto 0);
    signal btn_i : in std_logic_vector(3 downto 0)
    );
end Lab6;

architecture Behavioral of Lab6 is

    signal digit_i : std_logic_vector(31 downto 0):=(others => '1');
    signal clk_d : std_logic;

    component divider
    Port (
        signal clk_i : in std_logic;
      signal clk_o : out std_logic);
    end component;

    function digit(sw : in std_logic_vector(3 downto 0)) return std_logic_vector is
    begin
        case sw is
            when "0000" => return ("0000001");
            when "0001" => return ("1001111");
            when "0010" => return ("0010010");
            when "0011" => return ("0000110");
            when "0100" => return ("1001100");
            when "0101" => return ("0100100");
            when "0110" => return ("0100000");
            when "0111" => return ("0001111");
            when "1000" => return ("0000000");
            when "1001" => return ("0000100");
            when "1010" => return ("0000010");
            when "1011" => return ("1100000");
            when "1100" => return ("0110001");
            when "1101" => return ("1000010");
            when "1110" => return ("0110000");
            when others => return ("0111000");
        end case;
    end function digit;

BEGIN

    div:divider
    port map (  clk_i => clk_i,
                    clk_o => clk_d);

    process(clk_d)
    variable counter : integer := 0;
    begin
    if rising_edge(clk_d) then
        --AN3
        if btn_i(3) = '1' then
                digit_i(31 downto 25) <= digit(sw_i(3 downto 0));
        end if;
        -- AN2
        if btn_i(2) = '1' then
                digit_i(23 downto 17) <= digit(sw_i(3 downto 0));
        end if;
        -- AN1
        if btn_i(1) = '1' then
                digit_i(15 downto 9) <= digit(sw_i(3 downto 0));
        end if;
        -- AN0
        if btn_i(0) = '1' then
                digit_i(7 downto 1) <= digit(sw_i(3 downto 0));
        end if;
        digit_i(24) <= not sw_i(7);
        digit_i(16) <= not sw_i(6);
        digit_i(8) <= not sw_i(5);
        digit_i(0) <= not sw_i(4);

            if counter = 4 then
            counter := 0;
            elsif counter = 0 then
            led7_seg_o <= digit_i(31 downto 24);
            led7_an_o <= "0111";
            counter := counter +1;
            elsif counter = 1 then
            led7_seg_o <= digit_i(23 downto 16);
            led7_an_o <= "1011";
            counter := counter +1;
            elsif counter = 2 then
            led7_seg_o <= digit_i(15 downto 8);
            led7_an_o <= "1101";
            counter := counter +1;
            elsif counter = 3 then
            led7_seg_o <= digit_i(7 downto 0);
            led7_an_o <= "1110";
            counter := counter +1;
            end if;
    end if;
    end process;

END Behavioral;